Abstract is missing.
- Auto-parallelization of data structure operations for GPUsRupesh Nasre. 1-10 [doi]
- Heuristics for greedy transport triggered architecture interconnect explorationTimo Viitanen, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala. 1-7 [doi]
- A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCsKiran Chandramohan, Michael F. P. O'Boyle. 1-10 [doi]
- The improbable but highly appropriate marriage of 3D stacking and neuromorphic acceleratorsBilel Belhadj, Alexandre Valentian, Pascal Vivet, Marc Duranton, Liqiang He, Olivier Temam. 1-9 [doi]
- CAPED: Context-aware personalized display brightness for mobile devicesMatthew Schuchhardt, Susmit Jha, Raid Ayoub, Michael Kishinevsky, Gokhan Memik. 1-10 [doi]
- A low-cost memory interface for high-throughput acceleratorsJing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu. 1-10 [doi]
- Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulatorsHarry Wagstaff, Tom Spink, Björn Franke. 1-10 [doi]
- AdaPNet: Adapting process networks in response to resource variationsLars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele. 1-10 [doi]
- Automatic custom instruction identification in memory streaming algorithmsMartin Haab, Lars Bauer, Jörg Henkel. 1-9 [doi]
- Reducing cache leakage energy for hybrid SPM-cache architecturesHao Wen, Wei Zhang. 1-9 [doi]
- EnVM: Virtual memory design for new memory architecturesPooja Roy, Manmohan Manoharan, Weng-Fai Wong. 1-10 [doi]
- Fault resilient physical neural networks on a single chipWeidong Shi, Yuanfeng Wen, Ziyi Liu, Xi Zhao, Dainis Boumber, Ricardo Vilalta, Lei Xu. 1-10 [doi]
- A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoCMickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles. 1-10 [doi]
- A system-level simulation framework for evaluating task migration in MPSoCsWei Quan, Andy D. Pimentel. 1-9 [doi]
- SDCTune: A model for predicting the SDC proneness of an application for configurable protectionQining Lu, Karthik Pattabiraman, Meeta Sharma Gupta, Jude A. Rivers. 1-10 [doi]
- Team up: Cooperative memory management in embedded systemsIsabella Stilkerich, Philip Taffner, Christoph Erhardt, Christian Dietrich, Christian Wawersich, Michael Stilkerich. 1-10 [doi]
- A high-level model of embedded flash energy consumptionJames Pallister, Kerstin Eder, Simon J. Hollis, Jeremy Bennett. 1-9 [doi]
- COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systemsArtjom Grudnitsky, Lars Bauer, Jörg Henkel. 1-10 [doi]
- Energy-efficient VFI-partitioned multicore design using wireless NoC architecturesRyan Kim, Guangshuo Liu, Paul Wettin, Radu Marculescu, Diana Marculescu, Partha Pratim Pande. 1-9 [doi]
- Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applicationsNarasinga Rao Miniskar, Soma Kohli, Haewoo Park, Donghoon Yoo. 1-9 [doi]
- Context-sensitive timing simulation of binary embedded softwareSebastian Ottlik, Stefan Stattelmann, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann. 1-10 [doi]
- Splitting functions into single-entry regionsStefan Hepp, Florian Brandner. 1-10 [doi]
- Control-layer optimization for flow-based mVLSI microfluidic biochipsKai Hu, Trung Anh Dinh, Tsung-Yi Ho, Krishnendu Chakrabarty. 1-10 [doi]
- Construction of GCCFG for inter-procedural optimizations in Software Managed Manycore (SMM) architecturesBryce Holton, Ke Bai, Aviral Shrivastava, Harini Ramaprasad. 1-10 [doi]