Abstract is missing.
- FastCollect: offloading generational garbage collection to integrated GPUsAbhinav, Rupesh Nasre. [doi]
- A jump-target identification method for multi-architecture static binary translationAlessandro Di Federico, Giovanni Agosta. [doi]
- Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systemsThomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar. [doi]
- D-PUF: an intrinsically reconfigurable DRAM PUF for device authentication in embedded systemsSoubhagya Sutar, Arnab Raha, Vijay Raghunathan. [doi]
- Speculative disassembly of binary codeM. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz. [doi]
- Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chipPaolo Mantovani, Emilio G. Cota, Christian Pilato, Giuseppe Di Guglielmo, Luca P. Carloni. [doi]
- RRAM based learning accelerationYu Wang, Lixue Xia, Ming Cheng, Tianqi Tang, Boxun Li, Huazhong Yang. [doi]
- LOCUS: low-power customizable many-core architecture for wearablesCheng Tan, Aditi Kulkarni, Vanchinathan Venkataramani, Manupa Karunaratne, Tulika Mitra, Li-Shiuan Peh. [doi]
- Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platformsWonje Choi, Karthi Duraisamy, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Radu Marculescu, Diana Marculescu. [doi]
- COMET: communication-optimised multi-threaded error-detection techniqueKonstantina Mitropoulou, Vasileios Porpodas, Timothy M. Jones. [doi]
- On-the-fly load data value tracing in multicoresMounika Ponugoti, Amrish K. Tewar, Aleksandar Milenkovic. [doi]
- Power and thermal management in massive multicore chips: theoretical foundation meets architectural innovation and resource allocationPaul Bogdan, Partha Pratim Pande, Hussam Amrouch, Muhammad Shafique, Jörg Henkel. [doi]
- Enabling OpenVX support in mW-scale parallel acceleratorsGiuseppe Tagliavini, Germain Haugou, Andrea Marongiu, Luca Benini. [doi]
- CaffePresso: an optimized library for deep learning on embedded accelerator-based platformsGopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Nachiket Kapre. [doi]
- ILP-based modulo scheduling for high-level synthesisJulian Oppermann, Andreas Koch 0001, Melanie Reuter-Oppermann, Oliver Sinnen. [doi]
- Matrix multiplication beyond auto-tuning: rewrite-based GPU code generationMichel Steuwer, Toomas Remmelg, Christophe Dubach. [doi]
- Towards the design of fault-tolerant mixed-criticality systems on multicoresLuyuan Zeng, Pengcheng Huang, Lothar Thiele. [doi]
- Runtime management of adaptive MPSoCs for graceful degradationStavros Tzilis, Ioannis Sourdis, Vasileios Vasilikos, Dimitrios Rodopoulos, Dimitrios Soudris. [doi]
- Redesigning a tagless access buffer to require minimal ISA changesCarlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Själander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee. [doi]
- A real-time digital-microfluidic platform for epigeneticsMohamed Ibrahim, Craig Boswell, Krishnendu Chakrabarty, Kristin Scott, Miroslav Pajic. [doi]
- Neural network transformation under hardware constraintsYouhui Zhang, Yu Ji, Wenguang Chen, Yuan Xie. [doi]