Abstract is missing.
- Ispike: A Post-link Optimizer for the Intel®Itanium®ArchitectureChi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney. 15-26 [doi]
- Physical Experimentation with Prefetching Helper Threads on Intel s Hyper-Threaded ProcessorsDongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang 0003, Donald Yeung, Milind Girkar, John Paul Shen. 27-38 [doi]
- Compiler Optimization of Memory-Resident Value Communication Between Speculative ThreadsAntonia Zhai, Christopher B. Colohan, J. Gregory Steffan, Todd C. Mowry. 39-52 [doi]
- VHC: Quickly Building an Optimizer for Complex Embedded ArchitecturesMichael Dupré, Nathalie Drach, Olivier Temam. 53-64 [doi]
- SYZYGY - A Framework for Scalable Cross-Module IPOSungdo Moon, Xinliang D. Li, Robert Hundt, Dhruva R. Chakrabarti, Luis A. Lozano, Uma Srinivasan, Shin-Ming Liu. 65-74 [doi]
- LLVM: A Compilation Framework for Lifelong Program Analysis & TransformationChris Lattner, Vikram S. Adve. 75-88 [doi]
- Exploring Code Cache Eviction Granularities in Dynamic Optimization SystemsKim M. Hazelwood, James E. Smith. 89-99 [doi]
- Improving 64-Bit Java IPF Performance by Compressing Heap ReferencesAli-Reza Adl-Tabatabai, Jay Bharadwaj, Michal Cierniak, Marsha Eng, Jesse Fang, Brian T. Lewis, Brian R. Murphy, James M. Stichnoth. 100-110 [doi]
- A Dynamically Tuned Sorting LibraryXiaoming Li, María Jesús Garzarán, David A. Padua. 111-124 [doi]
- Software-Controlled Operand-GatingRamon Canal, Antonio González, James E. Smith. 125-136 [doi]
- Specialized Dynamic Optimizations for High-Performance Energy-Efficient MicroarchitectureYoav Almog, Roni Rosner, Naftali Schwartz, Ari Schmorak. 137-150 [doi]
- Probabilistic Predicate-Aware Modulo SchedulingMikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson. 151-162 [doi]
- Single-Dimension Software Pipelining for Multi-Dimensional LoopsHongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao. 163-174 [doi]
- Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional LoopsHongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao. 175-188 [doi]
- Exploring the Performance Potential of Itanium® Processors with ILP-based SchedulingSebastian Winkel. 189-200 [doi]
- FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized DatapathsManjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke. 201-212 [doi]
- Using Dynamic Binary Translation to Fuse Dependent InstructionsShiliang Hu, James E. Smith. 213-226 [doi]
- The Accuracy of Initial Prediction in Two-Phase Dynamic Binary TranslatorsYoufeng Wu, Mauricio Breternitz Jr., Justin Quek, Orna Etzion, Jesse Fang. 227-238 [doi]
- Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization SystemsRahul Joshi, Michael D. Bond, Craig B. Zilles. 239-250 [doi]
- Extending Path Profiling across Loop Backedges and Procedure BoundariesSriraman Tallam, Xiangyu Zhang, Rajiv Gupta. 251-264 [doi]
- Optimizing Translation Out of SSA Using Renaming ConstraintsFabrice Rastello, François de Ferrière, Christophe Guillon. 265-278 [doi]
- A Compiler Scheme for Reusing Intermediate Computation ResultsYonghua Ding, Zhiyuan Li. 279-290 [doi]
- Custom Data Layout for Memory ParallelismByoungro So, Mary W. Hall, Heidi E. Ziegler. 291-302 [doi]
- Static Identification of Delinquent LoadsVlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong. 303-314 [doi]
- Exposing Memory Access Regularities Using Object-Relative Memory ProfilingQiang Wu, Artem Pyatakov, Alexey Spiridonov, Easwaran Raman, Douglas W. Clark, David I. August. 315-324 [doi]