Table of Contents

• An active rectifier/regulator combo circuit for powering biomedical implantsEdward K. F. Lee. 1-4 [doi]
• A 10-MHz bandwidth 70-dB SNDR 640MS/s continuous-time ΣΔ ADC using Gm-C filter with nonlinear feedback DAC calibrationJiageng Huang, Shiliang Yang, George Jie Yuan. 1-4 [doi]
• Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectricsYoung Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra. 1-4 [doi]
• An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applicationsLeibo Liu, Chenchen Deng, Dong Wang, Min Zhu, Shouyi Yin, Peng Cao, Shaojun Wei. 1-4 [doi]
• Thermal noise modeling of nano-scale MOSFETs for mixed-signal and RF applicationsChih Hung Chen, David Chen, Ryan Lee, Peiming Lei, Daniel Wan. 1-8 [doi]
• A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detectorYao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan. 1-4 [doi]
• Wireline transmitter and receiver design techniquesDennis Michael Fischette, Jaeha Kim. 1 [doi]
• FireBird: PowerPC e200 based SoC for high temperature operationRadisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici. 1-4 [doi]
• A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failureMakoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, M. Tanaka, Shinji Tanaka, Koji Nii. 1-4 [doi]
• Circuit reliability simulation using TMI2Min-Chie Jeng, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin. 1-7 [doi]
• A split-foundry asynchronous FPGABenjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar. 1-4 [doi]
• Microsystems for biomedical and sensing applicationsChristophe Antoine, Stephen O'Driscoll. 1 [doi]
• A programmable analog frequency-locked loop for VCO characterization and test with 8 ppm resolutionSadok Aouini, Jean-Francois Bousquet, Naim Ben Hamida, Lukas Jakober, John Wolczanski, Christopher Kurowski. 1-4 [doi]
• Design metrics for blind ADC-based wireline receiversAli Sheikholeslami, Hirotaka Tamura. 1-8 [doi]
• A 9.2-GHz digital phase-locked loop with peaking-free transfer functionSigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim. 1-4 [doi]
• Foundations for scaling beyond 14nmRichard Schenker, Vivek Singh. 1-4 [doi]
• A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offsetJames S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada. 1-4 [doi]
• Trends, Possibilities and Limitations of Silicon Photonic Integrated Circuits and DevicesJohn Bowers. 1-89 [doi]
• Electrical and photonic I/O test and debugMike Li, Takahiro J. Yamaguchi. 1-2 [doi]
• Corner models: Inaccurate at best, and it only gets worst ..Colin C. McAndrew, Ik-Sung Lim, Brandt Braswell, Doug Garrity. 1-4 [doi]
• A 116nW multi-band wake-up receiver with 31-bit correlator and interference rejectionSeunghyun Oh, Nathan E. Roberts, David D. Wentzloff. 1-4 [doi]
• A/D converter circuit and architecture design for high-speed data communicationBoris Murmann. 1-78 [doi]
• SRAM read current variability and its dependence on transistor statisticsSriramkumar Venugopalan, Vivek Joshi, Luis Zamudio, Matthias Goldbach, Gert Burbach, Ralf Van Bentum, Sriram Balasubramanian. 1-4 [doi]
• Analog techniques IIHasnain Lakdawala, Eric Naviasky. 1 [doi]
• An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selectionMohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura. 1-8 [doi]
• A Verilog piecewise-linear analog behavior model for mixed-signal validationSabrina Liao, Mark Horowitz. 1-5 [doi]
• A 4-15-GHz ring oscillator based injection-locked frequency multiplier with built-in harmonic generationJie Xu, Jianyun Hu, Berkehan Ciftcioglu, Hui Wu. 1-4 [doi]
• Single-inductor-multiple-output DC-DC converter designPhilip K. T. Mok. 1-70 [doi]
• A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displaysMaofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong, Manoj Sachdev. 1-4 [doi]
• An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOSNan Qi, Baoyong Chi, Yang Xu, Zhou Chen, Jun Xie, Yang Xu, Zheng Song, Zhihua Wang. 1-4 [doi]
• Switched-capacitor filter based Type-III compensation for switched-mode Buck convertersGaurav Bawa, Alex Q. Huang. 1-4 [doi]
• A 40V 10W 93%-efficiency current-accuracy-enhanced dimmable LED driver with adaptive timing difference compensation for solid-state lighting applicationsDongkyung Park, Hoi Lee. 1-4 [doi]
• Concurrent design of ESD protection and ICs for optimization and predictionAlbert Wang. 1-34 [doi]
• A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLAKyoungtae Lee, Yeonam Yoon, Nan Sun. 1-4 [doi]
• CMOS low-power transceivers for 60GHz multi Gbit/s communicationsVojkan Vidojkovic, Viki Szortyka, Khaled Khalaf, Giovanni Mangraviti, Bertrand Parvais, Kristof Vaesen, Steven Brebels, Annachiara Spagnolo, Michael Libois, John R. Long, Kuba Raczkowski, Praveen Raghavan, André Bourdoux, Min Li, Charlotte Soens, Vito Giannini, Piet Wambacq. 1-8 [doi]
• Design for nanoscale patterningPuneet Gupta. 1-52 [doi]
• Compact high-power 60 GHz power amplifier in 65 nm CMOSPayam M. Farahabadi, Kambiz K. Moez. 1-4 [doi]
• An ultra-broadband compact mm-wave butler matrix in CMOS for array-based MIMO systemsJong Seok Park, Taiyun Chi, Hua Wang. 1-4 [doi]
• A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRRKhaled Abdelfattah, Sherif Galal, Iuri Mehr, Alex Jianzhong Chen, Ahmet Tekin, Xicheng Jiang, Todd Brooks. 1-4 [doi]
• A power sensor with 80ns response time for power management in microprocessorsSrikar Bhagavatula, Byunghoo Jung. 1-4 [doi]
• Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable MemoryIgor Arsovski, Travis Hebig, John Goss, Paul Grzymkowski, Josh Patch. 1-4 [doi]
• CMOS millimeter wave phase shifter based on tunable transmission linesWayne H. Woods, Alberto Valdes-Garcia, Hanyi Ding, Jay Rascoe. 1-4 [doi]
• Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive rangeGerrit den Besten, Harold G. Hanson, Ranjeet K. Gupta. 1-4 [doi]
• A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulationFei Chen, Yu Li, Deyuan Lin, Huiying Zhuo, Woogeun Rhee, Jongjin Kim, Dongwook Kim, Zhihua Wang. 1-4 [doi]
• Design techniques for CMOS backplane transceivers approaching 30-Gb/s data ratesJohn F. Bulzacchelli. 1-8 [doi]
• From 2D-planar to 3D-non-planar device architecture: A scalable path forward?Ghavam G. Shahidi. 1-8 [doi]
• IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nmBarend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx. 1-4 [doi]
• A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structureShusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto. 1-4 [doi]
• A fast-locking digital DLL with a high resolution time-to-digital converterDandan Zhang, Hai-Gang Yang, Zhujia Chen, Wei Li, Zhihong Huang, Lijiang Gao, Wen-rui Zhu. 1-4 [doi]
• 40V MESFETs fabricated on 32nm SOI CMOSWilliam Lepkowski, Seth J. Wilk, J. Kam, Trevor J. Thornton. 1-4 [doi]
• Analog techniques IDon Thelen, Xicheng Jiang. 1 [doi]
• A fully integrated battery-connected switched-capacitor 4: 1 voltage regulator with 70% peak efficiency using bottom-plate charge recyclingTao Tong, Xuan Zhang, Wonyoung Kim, David Brooks, Gu-Yeon Wei. 1-4 [doi]
• BIF - Battery interface standard for mobile devicesWolfgang Furtner, Stephan Schacher, Markus Littow, Lionel Cimaz, Pekka E. Leinonen. 1-8 [doi]
• Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy ditheringGuanhua Wang, Yun Chiu. 1-4 [doi]
• A reconfigurable ΔΣ modulator with up to 100 MHz bandwidth using flash reference shufflingTrevor C. Caldwell, David Alldred, Zhao Li. 1-4 [doi]
• Sampling circuits that break the kT/C thermal noise limitRon Kapusta, Haiyang Zhu, Colin Lyden. 1-6 [doi]
• AMS system simulation techniquesLarry Nagel, Colin McAndrew. 1 [doi]
• All-digital 90° phase-shift DLL with a dithering jitter suppression schemeDong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Won Lee, Seong-Ook Jung. 1-4 [doi]
• High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safetyLei Wan, Yajie Qin, Patrick Chiang, Guoping Chen, Ran Liu, Zhiliang Hong. 1-4 [doi]
• Algorithmic nonlinear macromodeling: Challenges, solutions and applications in Analog/Mixed-Signal validationChenjie Gu. 1-8 [doi]
• 45pW ESD clamp circuit for ultra-low power applicationsYen-Po Chen, Yoonmyung Lee, Jae-Yoon Sim, Massimo Alioto, David Blaauw, Dennis Sylvester. 1-4 [doi]
• An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOSKhurram Muhammad, Ming-Cho Chen, Kai-Hung Wang, Kuang-Ping Ma, Yu-Lin Hiseh, Wei-Show Hsu, Yuan-Yu Fu, Meng-Chang Lee, Shuo-Yuan Hsiao, Chih-Ming Hung. 1-4 [doi]
• Blind background calibration of harmonic distortion based on selective samplingManideep Gande, Ho-Young Lee, Hariprasath Venkatram, Jon Guerber, Un-Ku Moon. 1-4 [doi]
• A 15-bit binary-weighted current-steering DAC with ordered element matchingTao Zeng, Kevin Townsend, Jingbo Duan, Degang Chen. 1-4 [doi]
• Event-driven simulation of Volterra series models in SystemVerilogJi-Eun Jang, Si-Jung Yang, Jaeha Kim. 1-4 [doi]
• Design considerations for low-power receiver front-end in high-speed data linksSudip Shekhar, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper. 1-8 [doi]
• 2 per MBMing-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong. 1-4 [doi]
• A stackable switched-capacitor DC/DC converter IC for LED drivers with 90% efficiencyChengrui Le, Mitchell Kline, Daniel L. Gerber, Seth R. Sanders, Peter R. Kinget. 1-4 [doi]
• A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signalBongjin Kim, Weichao Xu, Chris H. Kim. 1-4 [doi]
• The past present and future of design-technology co-optimizationGreg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken. 1-8 [doi]
• A fully integrated highly linear receiver with automatic IP2 calibration schemes for multi-standard applicationsAshkan Borna, Yanjie Wang, Christopher D. Hull, Hua Wang, Ali Niknejad. 1-4 [doi]
• A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDCTetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada. 1-4 [doi]
• Structure-aware high-dimensional performance modeling for analog and mixed-signal circuitsShupeng Sun, Xin Li, Chenjie Gu. 1-4 [doi]
• ST-MRAM fundamentals, challenges, and applicationsT. Andre, S. M. Alam, D. Gogl, C. K. Subramanian, H. Lin, W. Meadows, X. Zhang, N. D. Rizzo, J. Janesky, D. Houssameddine, J. M. Slaughter. 1-8 [doi]
• A novel OTA-based fast lock PLLMezyad Amourah, Sandeep Krishnegowda, Morgan Whately. 1-4 [doi]
• A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOSPraveen Kumar Sharma, Mike Shuo-Wei Chen. 1-4 [doi]
• A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOIMihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman. 1-4 [doi]
• A general-purpose vision processor with 160×80 pixel-parallel SIMD processor arrayAlexey Lopich, Piotr Dudek. 1-4 [doi]
• Mismatch characterization of small metal fringe capacitorsVaibhav Tripathi, Boris Murmann. 1-4 [doi]
• Charge steering: A low-power design paradigmBehzad Razavi. 1-8 [doi]
• A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocationMuhammad Ahmadi, Won Namgoong. 1-4 [doi]
• Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-endZhimiao Chen, Yifan Wang, Joern Driesen, Fabio Garzia, Stefan Koehler, Frank Henkel, Ralf Wunderlich, Stefan Heinen. 1-4 [doi]
• Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor arrayQ. Guo, Michael A. Suster, R. Surapaneni, Carlos H. Mastrangelo, Darrin J. Young. 1-4 [doi]
• Power management circuits for a 15-μA, implantable pressure sensorSteve J. A. Majerus, Steven L. Garverick. 1-4 [doi]
• A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-designX. Shawn Wang, Xin Wang, Fei Lu, Li Wang, Rui Ma, Zongyu Dong, Li Sun, Albert Z. Wang, C. Patrick Yue, Dawn Wang, Alvin Joseph. 1-4 [doi]
• Prospective for nanowire transistorsJean-Pierre Colinge, Sang H. Dhong. 1-8 [doi]
• A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADCZule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa. 1-4 [doi]
• Discretization and discrimination methods for design, verification, and testing of analog/mixed-signal circuitsJaeha Kim, Jiho Lee, Do-Gyoon Song, Taehwan Kim, Kyung-Hoon Kim, Seobin Jung, Sangho Youn. 1-8 [doi]
• A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillatorWonsik Yu, KwangSeok Kim, SeongHwan Cho. 1-4 [doi]
• A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliersAlvin Li, Shiyuan Zheng, Jun Yin, Howard C. Luong, Xun Luo. 1-4 [doi]
• A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applicationsBurak Çatli, Ali Nazemi, Tamer Ali, Siavash Fallahi, Yang Liu, Jaehyup Kim, Mohammed M. Abdul-Latif, Mahmoud Reza Ahmadi, Hassan Maarefi, Afshin Momtaz, Namik Kocaman. 1-4 [doi]
• Advanced digital phase-locked loopsSalvatore Levantino. 1-95 [doi]
• A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applicationsSang-Soo Lee, Edward Boling, Augustine Kuo, Robert Rogenmoser. 1-4 [doi]
• A 11μW Sub-pJ/bit reconfigurable transceiver for mm-sized wireless implantsAnatoly Yakovlev, Jihoon Jang, Daniel Pivonka, Ada S. Y. Poon. 1-4 [doi]
• A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switchingYung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li. 1-4 [doi]
• Energy centric model of SRAM write operation for improved energy and error ratesSwaroop Ghosh. 1-4 [doi]
• Capacitive proximity communication with distributed alignment sensing for origami biomedical implantsMatthew Loh, Azita Emami-Neyestanak. 1-4 [doi]
• A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithmsShuai Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng. 1-4 [doi]
• Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body biasV. Agrawal, N. Kepler, David Kidd, G. Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, T. Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama. 1-4 [doi]
• A -173 dBc/Hz @ 1 MHz offset Colpitts oscillator using AlN contour-mode MEMS resonatorJabeom Koo, Augusto Tazzoli, Jeronimo Segovai-Fernandez, Gianluca Piazza, Brian P. Otis. 1-4 [doi]
• Transformer-based dual-band VCO and ILFD for wide-band mm-Wave LO generationYue Chao, Howard C. Luong. 1-4 [doi]
• Energy-efficient recognition and mining processor using scalable effort designVinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan. 1-4 [doi]
• A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping techniqueJian Xu, Zhi Yang. 1-4 [doi]
• Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)Mike Peng Li, Masashi Shimanouchi, Hsinho Wu. 1-8 [doi]
• AMS verification in advanced technologiesHidetoshi Onodera, Yu Kevin Cao. 1 [doi]
• Power managementChristoph Sandner, Rajeevan Amirtharajah. 1 [doi]
• Parallel gain enhancement technique for switched-capacitor circuitsHariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon. 1-4 [doi]
• AOT-controlled dual-mode AVP buck regulator with AEAF mechanismHsin-Lun Li, Chia-Cheng Pao, Bo-Ming Chen, Chien-Hung Tsai. 1-4 [doi]
• A 110nA synchronous boost regulator with autonomous bias gating for energy harvestingKhondker Z. Ahmed, Saibal Mukhopadhyay. 1-4 [doi]
• A broadband biosensor interface IC for miniaturized dielectric spectroscopy from MHz to GHzMehran Bakhshiani, Michael A. Suster, Pedram Mohseni. 1-4 [doi]
• A model-agnostic technique for simulating per-element distortion contributionsNagendra Krishnapura, K. S. Rakshitdatta. 1-4 [doi]
• A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard codingVahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici. 1-4 [doi]
• Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memoryKen Takeuchi. 1-6 [doi]
• High-speed wireline timing recovery & PLLsSamuel Palermo, Kimo Tam. 1 [doi]
• A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opampsMaarten De Bock, Pieter Rombouts. 1-4 [doi]
• How to reduce power in 3D IC designs: A case study with OpenSPARC T2 coreMoongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim. 1-4 [doi]
• Advanced memory topicsKoji Niii, Toshiaki Kirihata. 1 [doi]
• A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applicationsSeung-hwan Song, Ki Chul Chun, Chris H. Kim. 1-4 [doi]
• A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOBYida Duan, Elad Alon. 1-4 [doi]
• A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppressionMing-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou. 1-4 [doi]
• Energy efficient SoC designVisvesh Sathe, Arif Rahman. 1 [doi]
• Variation and analog modelingTrent McConaghy, Brian Chen. 1 [doi]
• Low power chip & system design for biomedicai applicationsBrian Otis. 1-53 [doi]
• A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOSSiva V. Thyagarajan, Ali M. Niknejad, Christopher D. Hull. 1-4 [doi]
• A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital controlSakshi Arora, David K. Su, Bruce A. Wooley. 1-4 [doi]
• Advances in the design of wideband receiversDavid Murphy, Mohyee Mikhemar, Ahmad Mirzaei, Hooman Darabi. 1-8 [doi]
• Estimation of passive mixer output bandwidth using switched-capacitor techniquesEssam S. Atalla, Frank Zhang, Abdellatif Bellaouar, Poras T. Balsara. 1-4 [doi]
• A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOSJingjing Chen, Weiyang Liu, Peng Feng, Haiyong Wang, Nanjian Wu. 1-4 [doi]
• Characterization of matching variability and low-frequency noise for mixed-signal technologiesHans Tuinhout. 1-111 [doi]
• A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOSRune Kaald, Bjørnar Hernes, Christian Holdo, Frode Telstø, Ivar Lokken. 1-4 [doi]
• Highly efficient CMOS rectifier assisted by symmetric and voltage-boost PV-cell structures for synergistic ambient energy harvestingKoji Kotani. 1-4 [doi]
• Indirect performance sensing for on-chip analog self-healing via Bayesian model fusionS. Sun, F. Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman. 1-4 [doi]
• Distributed clock generator for synchronous SoC using ADPLL networkEldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, C. Shan, O. Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard. 1-4 [doi]
• A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operationShidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull. 1-4 [doi]
• Interconnect and package design of a heterogeneous stacked-silicon FPGAEphrem Wu, Khaldoon Abugharbieh, Bahareh Banijamali, Suresh Ramalingam, Paul Wu, Chris Wyland. 1-8 [doi]
• Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologiesGeert Hellings, Shih-Hung Chen, Dimitri Linten, Mirko Scholz, Guido Groeseneken. 1-4 [doi]
• A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOSJae-Won Nam, David Chiong, Mike Shuo-Wei Chen. 1-4 [doi]
• SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm processLeibo Liu, Weilong Zhang, Chenchen Deng, Shouyi Yin, Shanshan Cai, Shaojun Wei. 1-4 [doi]
• A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearizationAbhishek Ghosh, Sudhakar Pamarti. 1-4 [doi]
• Scalable behavior modeling for 3D field-programmable ESD protection structuresL. Wang, X. Wang, Z. T. Shi, R. Ma, C. Zhang, Z. Dong, F. Lu, H. Zhao, A. Wang. 1-4 [doi]
• A bipolar >40-V driver in 45-nm SOI CMOS technologyYousr Ismail, Chang Jin Kim, Chih-Kong Ken Yang. 1-4 [doi]
• 65nW CMOS temperature sensor for ultra-low power microsystemsSeokhyeon Jeong, Jae-Yoon Sim, David Blaauw, Dennis Sylvester. 1-4 [doi]
• Hybrid transformer-based tunable integrated duplexer with antenna impedance tracking loopSherif H. Abdelhalem, Prasad S. Gudem, Lawrence E. Larson. 1-4 [doi]
• Design for manufacturing layout analyses correlate layout to physico-chemical yield loss mechanismsChristine P. Tan, Congshu Zhou, Yi Tian, Chang Liu, Hein-Mun Lam, Jian Zhang, Mark Lu. 1-4 [doi]
• Nyquist rate A/D convertersMohammad Ranjbar, John McNeill. 1 [doi]
• A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiersJames Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa. 1-4 [doi]
• A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined schemeKai Li, Mitsuyoshi Ito, Atsushi Esumi. 1-3 [doi]
• A monolithic digitally controlled ripple-based DC-DC converter with digital inductor current sensorMan Pun Chan, Philip K. T. Mok. 1-4 [doi]
• A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power convertersZhidong Liu, Hoi Lee. 1-4 [doi]
• Recent advances in GaN power electronicsKarim Boutros, Rongming Chu, Brian Hughes. 1-4 [doi]
• A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applicationsAliakbar Homayoun, Behzad Razavi. 1-4 [doi]
• Gate stack resistance and limits to CMOS logic performanceR. A. Wachnik, S. Lee, L. H. Pan, N. Lu, H. Li, R. Bingert, M. Randall, S. Springer, C. Putnam. 1-4 [doi]
• Analysis of deviation from Pelgrom scaling law in Vth variability of pocket-implanted MOSFETKiyohiko Sakakibara, Yaichiro Miura, Toshio Kumamoto, Susumu Tanimoto. 1-4 [doi]
• Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-ratingBharan Giridhar, Matthew Fojtik, David Fick, Dennis Sylvester, David Blaauw. 1-4 [doi]
• A 5GS/s 4-bit time-based single-channel CMOS ADC for radio astronomyAndrew R. Macpherson, James W. Haslett, Leonid Belostotski. 1-4 [doi]
• A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOSJun Li, Hirohito Mukai, Mehmet Parlak, Michiaki Matsuo, James F. Buckwalter. 1-4 [doi]
• A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCsXiaochen Yang, Robert Payne, Jin Liu. 1-4 [doi]
• An 8-Bit 4-GS/s 120-mW CMOS ADCHegong Wei, Peng Zhang, Bibhu Datta Sahoo, Behzad Razavi. 1-4 [doi]
• A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-lineShunli Ma, Wei Fei, Hao Yu, Junyan Ren. 1-4 [doi]
• A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOSShuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang. 1-4 [doi]
• Oversampled ADC'sEric Naviasky, Hasnain Lakdawala. 1 [doi]
• Nonlinearity cancellation in digital PLLs (Invited paper)Salvatore Levantino, Carlo Samori. 1-8 [doi]
• A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitterSaurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu. 1-4 [doi]
• RF building blocksAndrea Mazzanti, Earl McCune. 1 [doi]
• A fully differential ultra-compact broadband transformer based quadrature generation schemeJong Seok Park, Shouhei Kousai, Hua Wang. 1-4 [doi]
• Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOSXuan Zhang, Tao Tong, David Brooks, Gu-Yeon Wei. 1-4 [doi]
• An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillatorTetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada. 1-4 [doi]
• Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitorTakao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka. 1-4 [doi]
• A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rateSedigheh Hashemi, Behzad Razavi. 1-4 [doi]
• A lumped component programmable delay element for Ultra-Wideband beamformingNaga Rajesh, Shanthi Pavan. 1-4 [doi]