Table of Contents

• An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State MachinesTam Anh Chu, Narayana Mani, Clement K. C. Leung. 2-6 [doi]
• Elimination of Dynamic hazards by FactoringCho W. Moon, Robert K. Brayton. 7-13 [doi]
• Optimized State Assignment of single fault Tolerant FSMs Based on SEC CodesRégis Leveugle. 14-18 [doi]
• Minimal Shift Counters and Frequency DivisionAlice M. Tokarnia. 19-24 [doi]
• Algorithms for Approximate FSM TraversalHyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi. 25-30 [doi]
• SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism AlgorithmMiles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather. 31-37 [doi]
• HV/VH Trees: A New Spatial Data Structure for Fast Region QueriesGlenn G. Lai, Donald S. Fussell, D. F. Wong. 43-47 [doi]
• Increasing Design Quality and Engineering Productivity through Design ReuseEmil F. Girczyc, Steve Carlson. 48-53 [doi]
• Spectral Transforms for Large Boolean Functions with Applications to Technology MappingEdmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang. 54-60 [doi]
• Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous DesignsPolly Siegel, Giovanni De Micheli, David L. Dill. 61-67 [doi]
• Technology Mapping for Lower PowerVivek Tiwari, Pranav Ashar, Sharad Malik. 74-79 [doi]
• ::::INCREDYBLE-TG::::: INCREmental DYnamic test generation based on LEarningIrith Pomeranz, Sudhakar M. Reddy. 80-85 [doi]
• Automatic Functional Test Generation Using the Extended Finite State Machine ModelKwang-Ting Cheng, A. S. Krishnakumar. 86-91 [doi]
• Speed up of Behavioral A.T.P.G. using a Heuristic CriterionJean François Santucci, Anne-lise Courbis, Norbert Giambiasi. 92-96 [doi]
• Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic CircuitsSeiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy. 102-106 [doi]
• Sequential Circuit Test Generation on a Distributed SystemPrathima Agrawal, Vishwani D. Agrawal, Joan Villoldo. 107-111 [doi]
• VIPER: An Efficient Vigorously Sensitizable Path ExtractorHoon Chang, Jacob A. Abraham. 112-117 [doi]
• A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path ProblemShiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu. 118-122 [doi]
• A Verification Technique for Gated ClockMasamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli. 123-127 [doi]
• Circuit Delay Models and Their Exact Computation Using Timed Boolean FunctionsWilliam K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 128-134 [doi]
• Timing Optimization By Gate Resizing And Critical Path IdentificationWen-Ben Jone, Chen-Liang Fang. 135-140 [doi]
• What is the Next Big Productivity Boost for Designers? (Panel Abstract)Kurt Keutzer. 141 [doi]
• Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating TolerancesHelmut E. Graeb, Claudia U. Wieser, Kurt Antreich. 142-147 [doi]
• A New Optimizer for Performance Optimization of Analog Integrated CircuitsN. S. Nagaraj. 148-153 [doi]
• Performance-Constrained Worst-Case Variability Minimization of VLSI CircuitsAbhijit Dharchoudhury, Sung-Mo Kang. 154-158 [doi]
• Analog System Verification in the Presence of Parasitics Using Behavioral SimulationEdward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli. 159-163 [doi]
• Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract)Jonathan Rose. 164 [doi]
• Reliable Non-Zero Skew Clock Trees Using Wire Width OptimizationSatyamurthy Pullela, Noel Menezes, Lawrence T. Pillage. 165-170 [doi]
• Performance Oriented Rectilinear Steiner TreesAndrew Lim, Siu-Wing Cheng, Ching-Ting Wu. 171-176 [doi]
• Performance-Driven Steiner Tree Algorithm for Global RoutingXianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang. 177-181 [doi]
• High-Performance Routing Trees With Identified Critical SinksKenneth D. Boese, Andrew B. Kahng, Gabriel Robins. 182-187 [doi]
• The Sea-of-Wires Array Aynthesis SystemIng-Yi Chen, Geng-Lin Chen, Fredrick J. Hill, Sy-Yen Kuo. 188-193 [doi]
• Experiences in Functional Validation of a High Level Synthesis SystemRanga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru. 194-201 [doi]
• An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.Nam Sung Woo, Jaeseok Kim. 202-207 [doi]
• Performance Directed Technology Mapping for Look-Up Table Based FPGAsPrashant Sawkar, Donald E. Thomas. 208-212 [doi]
• On Area/Depth Trade-off in LUT-Based FPGA Technology MappingJason Cong, Yuzheng Ding. 213-218 [doi]
• MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAsMahesh Mehendale. 219-223 [doi]
• Sequential Synthesis for Table Look Up Programmable Gate ArraysRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 224-229 [doi]
• Non-Scan Design-for-Testability Techniques for Sequential CircuitsVivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel. 236-241 [doi]
• An Efficient Partitioning Strategy for Pseudo-Exhaustive TestingRajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer. 242-248 [doi]
• Partial Scan with RetimingDimitrios Kagaris, Spyros Tragoudas. 249-254 [doi]
• A Cost-Based Approach to Partial ScanPrashant S. Parikh, Miron Abramovici. 255-259 [doi]
• On Computing the Transitive Closure of a State Transition RelationYusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton. 260-265 [doi]
• Reducing BDD Size by Exploiting Functional DependenciesAlan J. Hu, David L. Dill. 266-271 [doi]
• Zero-Suppressed BDDs for Set Manipulation in Combinatorial ProblemsShin-ichi Minato. 272-277 [doi]
• A Layout Estimation Algorithm for RTL DatapathsMehrdad Nourani, Christos A. Papachristou. 285-291 [doi]
• Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan EnvironmentsTien-Chien Lee, Niraj K. Jha, Wayne Wolf. 292-297 [doi]
• Utilization of Multiport Memories in Data Path SynthesisTaewhan Kim, C. L. Liu. 298-302 [doi]
• Architectural Synthesis of Performance-Driven Multipliers with Accumulator InterleavingDebabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy. 303-307 [doi]
• Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora s Box? (Panel Abstract)Wayne Wolf. 308 [doi]
• Optimal Clustering for Delay MinimizationRajmohan Rajaraman, D. F. Wong. 309-314 [doi]
• Cost Minimization of Partitions into Multiple DevicesRoman Kuznar, Franc Brglez, Krzysztof Kozminski. 315-320 [doi]
• Iterative Wirability and Performance Improvement for FPGAsSudip Nag, Kaushik Roy. 321-325 [doi]
• On Routability Prediction for Field-Programmable Gate ArraysPak K. Chan, Martine D. F. Schlag, Jason Y. Zien. 326-330 [doi]
• High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip ModulesHaigeng Wang, Nikil D. Dutt, Alexandru Nicolau, Kai-Yeung Siu. 336-342 [doi]
• An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level DecompositionAbhijit Chatterjee, Rabindra K. Roy. 343-348 [doi]
• InSyn: Integrated Scheduling for DSP ApplicationsAlok Sharma, Rajiv Jain. 349-354 [doi]
• Estimating Architectural Resources and Performance for High-Level Synthesis ApplicationsAlok Sharma, Rajiv Jain. 355-360 [doi]
• Performance Enhancement of CMOS VLSI Circuits by Transistor ReorderingBradley S. Carlson, C. Y. Roger Chen. 361-366 [doi]
• Evaluation of Parts by Mixed-Level DC-Connected Components in Logic SimulationDah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh. 367-372 [doi]
• Comparative Design Validation Based on Event Pattern MappingsBenoit A. Gennart. 373-378 [doi]
• Improved Techniques for Probabilistic Simulation Including Signal Correlation EffectsGeorgios I. Stamoulis, Ibrahim N. Hajj. 379-383 [doi]
• Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational CircuitsHarish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj. 384-388 [doi]
• MSTC: A Method for Identifying Overconstraints during Hierarchical CompactionCyrus Bamji, Ravi Varadarajan. 389-394 [doi]
• Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LPSo-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo. 395-400 [doi]
• Optimal Graph Constraint Reduction for Symbolic Layout CompactionPeichen Pan, Sai-keung Dong, C. L. Liu. 401-406 [doi]
• A Compaction Method for Full Chip VLSI LayoutsJoseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori. 407-412 [doi]
• High-Level Transformations for Minimizing Syntactic VariancesViraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran. 413-418 [doi]
• High-Level Symbolic Construction Technique for High Performance Sequential SynthesisAndrew Seawright, Forrest Brewer. 424-428 [doi]
• High-Level Synthesis of Fault-Secure MicroarchitecturesRamesh Karri, Alex Orailoglu. 429-433 [doi]
• NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational CircuitsIrith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri. 439-445 [doi]
• Delay Fault Coverage and Performance TradeoffsWilliam K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 446-452 [doi]
• Design for Testability for Path Delay faults in Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. 453-457 [doi]
• Bridge Fault simulation strategies for CMOS integrated CircuitsBrian Chess, Tracy Larrabee. 458-462 [doi]
• Minimum Length Synchronizing Sequences of Finite State MachineJune-Kyung Rho, Fabio Somenzi, Carl Pixley. 463-468 [doi]
• Linking BDD-Based Symbolic Evaluation to Interactive Theorem-ProvingJeffrey J. Joyce, Carl-Johan H. Seger. 469-474 [doi]
• A Unified Approach to Language Containment and Fair CTL Model CheckingRamin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan. 475-481 [doi]
• Sequential Circuit Delay optimization Using Global Path DelaysSrimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler. 483-489 [doi]
• Resynthesis of Multi-Phase PipelinesNarendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 490-496 [doi]
• TIM: A Timing Package for Two-Phase, Level-Clocked CircuitryMarios C. Papaefthymiou, Keith H. Randall. 497-502 [doi]
• Diagnosis and Correction of Logic Design Errors in Digital CircuitsPi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj. 503-508 [doi]
• DRAFTS: Discretized Analog Circuit Fault SimulatorNaveena Nagi, Abhijit Chatterjee, Jacob A. Abraham. 509-514 [doi]
• Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level AccuracyWolfgang Meyer, Raul Camposano. 515-519 [doi]
• An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational CircuitsSreejit Chakravarty, Yiming Gong. 520-524 [doi]
• ::::Prime::::: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network ApproachTakeo Hamada, Chung-Kuan Cheng, Paul M. Chau. 531-536 [doi]
• A Nuffer Distribution Algorithm for High-Speed Clock RoutingJun Dong Cho, Majid Sarrafzadeh. 537-543 [doi]
• Cooperative Approach to a Practical Analog LSI Layout SystemMasato Mogaki, Youichi Shiraishi, Mitsuyuki Kimura, Tetsuro Hino. 544-549 [doi]
• Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC MicroprocessorGopi Ganapathy, Jacob A. Abraham. 550-555 [doi]
• ABLE: AMD Backplane for Layout EnginesKenneth W. Wan, Roshan A. Gidwani. 556-560 [doi]
• Practical Statistical Design of Complex Integrated Circuit ProductsSteven G. Duvall. 561-565 [doi]
• Rotation Scheduling: A Loop Pipelining AlgorithmLiang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha. 566-572 [doi]
• Critical Path Minimization Using Retiming and Algebraic Speed-UpZia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker. 573-577 [doi]
• A Tree-Based Scheduling Algorithm for Control-Dominated CircuitsS. H. Huang, Y.-L. Jeang, C. T. Hwang, Y. C. Hsu, J. F. Wang. 578-582 [doi]
• Synthesis of Pipelined Instruction Set ProcessorsRichard J. Cloutier, Donald E. Thomas. 583-588 [doi]
• Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible? (Panel Abstract)Michael C. McFarland. 589 [doi]
• An Efficient Multilayer MCM Router Based on Four-Via RoutingKei-Yong Khoo, Jason Cong. 590-595 [doi]
• An Efficient Timing-Driven Global Routing AlgorithmJin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh. 596-600 [doi]
• A Negative Reinforcement Method for PGA RoutingForbes D. Lewis, Wang Chia-Chi Pong. 601-605 [doi]
• Performance-Driven Interconnect Design Based on Distributed RC Delay ModelJason Cong, Kwok-Shing Leung, Dian Zhou. 606-611 [doi]
• A Clustering-Based Optimization Algorithm in Zero-Skew RoutingsMasato Edahiro. 612-616 [doi]
• Multi-vendor Tool Integration Experiences (Panel Abstract)Ronald Collett. 617 [doi]
• Espresso-Signature: A New Exact Minimizer for Logic FunctionsPatrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 618-624 [doi]
• A New Viewpoint on Two-Level Logic MinimizationOlivier Coudert, Jean Christophe Madre, Henri Fraisse. 625-630 [doi]
• Optimization of Combinational Logic Circuits Based on Compatible GatesMaurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli. 631-636 [doi]
• Optimization and Resynthesis of Complex Data-PathsHans Eveking, Stefan Höreth. 637-641 [doi]
• BDD Based Decomposition of Logic Functions with Application to FPGA SynthesisYung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula. 642-647 [doi]
• Design Management Using Dynamically Defined FlowsPeter R. Sutton, Jay B. Brockman, Stephen W. Director. 648-653 [doi]
• Active Documentation: A New Interface for VLSI DesignMário J. Silva, Randy H. Katz. 654-660 [doi]
• Performance Specification Using Attributed GrammarsRam Mandayam, Ranga Vemuri. 661-667 [doi]
• An Information Model of TimeCristian A. Giumale, Hilary J. Kahn. 668-672 [doi]
• FastHenry: A Multipole-Accelerated 3-D Inductance Extraction ProgramMattan Kamon, Michael J. Tsuk, Jacob White. 678-683 [doi]
• High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element MethodsTai-Yu Chou, Jay Cosentino, Zoltan J. Cendes. 684-690 [doi]
• Fast Approximation of the Transient Response of Lossy Transmision Line TreesMysore Sriram, Sung-Mo Kang. 691-696 [doi]
• Analysis and Reliable Design of ECL Circuits with Distributed RLC InterconnectionsMonjurul Haque, Salim Chowdhury. 697-701 [doi]
• An Efficient Non-Quasi-Static Diode Model for Circuit SimulationAndrew T. Yang, Yu Liu, Jack T. Yao, R. R. Daniels. 720-725 [doi]
• S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial FunctionHaifang Liao, Wayne Wei-Ming Dai, Rui Wang, Fung-Yuel Chang. 726-731 [doi]
• Addressing High-Speed Interconnect Issues in Asymptotic Waveform EvaluationEli Chiprout, Michel S. Nakhla. 732-736 [doi]
• Incremental Event-Driven Simulation of Digital FET CircuitsChandramouli Visweswariah, Jalal A. Wehbeh. 737-741 [doi]
• Where in the World Should CAD Software be Made? (Panel Abstract)John A. Darringer. 742 [doi]
• Geometric Embeddings for Faster and Better Multi-Way Netlist PartitioningCharles J. Alpert, Andrew B. Kahng. 743-748 [doi]
• Spectral ::::K::::-Way Ratio-Cut Partitioning and ClusteringPak K. Chan, Martine D. F. Schlag, Jason Y. Zien. 749-754 [doi]
• A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI DesignJason Cong, M Lissa Smith. 755-760 [doi]
• Quadratic Boolean Programming for Performance-Driven System PartitioningMinshine Shih, Ernest S. Kuh. 761-765 [doi]