Abstract is missing.
- How will the fabless model survive?Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu. 1-2 [doi]
- The good, the bad, and the ugly of silicon debugDoug Josephson. 3-6 [doi]
- A reconfigurable design-for-debug infrastructure for SoCsMiron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller. 7-12 [doi]
- Visibility enhancement for silicon debugYu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang. 13-18 [doi]
- A CPPLL hierarchical optimization methodology considering jitter, power and locking timeJun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann. 19-24 [doi]
- Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standardTom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen. 25-30 [doi]
- Generation of yield-aware Pareto surfaces for hierarchical circuit design space explorationSaurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar. 31-36 [doi]
- A real time budgeting method for module-level-pipelined bus based system using bus scenariosTadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino. 37-42 [doi]
- Exploiting forwarding to improve data bandwidth of instruction-set extensionsRamkumar Jayaseelan, Haibin Liu, Tulika Mitra. 43-48 [doi]
- Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchiesIlya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt. 49-52 [doi]
- Prototyping a fault-tolerant multiprocessor SoC with run-time fault recoveryXinping Zhu, Wei Qin. 53-56 [doi]
- Statistical analysis of SRAM cell stabilityKanak Agarwal, Sani R. Nassif. 57-62 [doi]
- Criticality computation in parameterized statistical timingJinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah. 63-68 [doi]
- Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure eventsRouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif. 69-72 [doi]
- An up-stream design auto-fix flow for manufacturability enhancementJie Yang, Ethan Cohen, Cyrus Tabery, Norma Rodriguez, Mark Craig. 73-76 [doi]
- The IC nanometer race -- what will it take to win? G. Singer, Philippe Magarshack, Dennis Buss, F.-C. Hsu, H.-K. Kang. 77-78 [doi]
- Use of C/C++ models for architecture exploration and verification of DSPsDavid Brier, Raj S. Mitra. 79-84 [doi]
- Maintaining consistency between systemC and RTL system designsAlistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard. 85-89 [doi]
- SystemC transaction level models and RTL verificationStuart Swan. 90-92 [doi]
- Towards a C++-based design methodology facilitating sequential equivalence checkingPhilippe Georgelin, Venkat Krishnaswamy. 93-96 [doi]
- Charge recycling in MTCMOS circuits: concept and analysisEhsan Pakbaznia, Farzan Fallah, Massoud Pedram. 97-102 [doi]
- Projection-based statistical analysis of full-chip leakage power with non-log-normal distributionsXin Li, Jiayong Le, Lawrence T. Pileggi. 103-108 [doi]
- Physical design methodology of power gating circuits for standard-cell-based designHyung-Ock Kim, Youngsoo Shin, Hyuk Kim, Iksoo Eo. 109-112 [doi]
- Challenges in sleep transistor design and implementation in low-power designsKaijian Shi, David Howard. 113-116 [doi]
- A fast simultaneous input vector generation and gate replacement algorithm for leakage power reductionLei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong. 117-120 [doi]
- Timing driven power gatingDe-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh. 121-124 [doi]
- A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space explorationIyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev. 125-130 [doi]
- An automated, reconfigurable, low-power RFID tagAlex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle. 131-136 [doi]
- Design space exploration and prototyping for on-chip multimedia applicationsHyung Gyu Lee, Ümit Y. Ogras, Radu Marculescu, Naehyuck Chang. 137-142 [doi]
- Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCsKuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen. 143-148 [doi]
- Refined statistical static timing analysis throughBenjamin N. Lee, Li-C. Wang, Magdy S. Abadir. 149-154 [doi]
- Statistical timing analysis with correlated non-gaussian parameters using independent component analysisJaskirat Singh, Sachin S. Sapatnekar. 155-160 [doi]
- Statistical timing based on incomplete probabilistic descriptions of parameter uncertaintyWei-Shen Wang, Vladik Kreinovich, Michael Orshansky. 161-166 [doi]
- Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD toolsAmith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar. 167-172 [doi]
- Decision-making for complex SoCs in consumer electronic productsRon Wilson, Yervant Zorian. 173 [doi]
- Entering the hot zone: can you handle the heat and be cool?A. Yang, R. Chandra, S. Burke, J. A. DeLaCruz, S. Santhanam, U. Ko. 174-175 [doi]
- Reliability challenges for 45nm and beyondJ. W. McPherson. 176-181 [doi]
- Design tools for reliability analysisZhihong Liu, Bruce McGaughy, James Z. Ma. 182-187 [doi]
- Design in reliability for communication designsUday Reddy Bandi, Murty Dasaka, Pavan K. Kumar. 188-192 [doi]
- Practical aspects of reliability analysis for IC designsT. Pompl, C. Schlünder, M. Hommel, H. Nielen, J. Schneider. 193-198 [doi]
- Power grid physics and implications for CADSanjay Pant, Eli Chiprout. 199-204 [doi]
- Fast analysis of structured power grid by triangularization based structure preserving model order reductionHao Yu, Yiyu Shi, Lei He. 205-210 [doi]
- Stochastic variational analysis of large power grids considering intra-die correlationsPraveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda. 211-216 [doi]
- A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programmingMin Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu. 217-222 [doi]
- Distributed dynamic BDD reorderingZiv Nevo, Monica Farkash. 223-228 [doi]
- SAT sweeping with local observability don t-caresQi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli. 229-234 [doi]
- Predicate learning and selective theory deduction for a difference logic solverChao Wang, Aarti Gupta, Malay K. Ganai. 235-240 [doi]
- Fast illegal state identification for improving SAT-based inductionVishnu C. Vimjam, Michael S. Hsiao. 241-246 [doi]
- A multi-port current source model for multiple-input switching effects in CMOS library cellsChirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout. 247-252 [doi]
- Statistical logic cell delay analysis using a current-based modelHanif Fatemi, Shahin Nazarian, Massoud Pedram. 253-256 [doi]
- Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncationN. Wong, V. Balakrishnan. 257-260 [doi]
- A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencilsN. Wong, C.-K. Chu. 261-266 [doi]
- Model order reduction of linear networks with massive ports via frequency-dependent port packingPeng Li, Weiping Shi. 267-272 [doi]
- Tradeoffs and choices for emerging SoCs in high-end applicationsNic Mokhoff, Yervant Zorian. 273 [doi]
- Overview of the MPSoC design challengeGrant Martin. 274-279 [doi]
- Programming models and HW-SW interfaces abstraction for multi-processor SoCAhmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot. 280-285 [doi]
- System-level exploration tools for MPSoC designsPeter Flake, Simon J. Davidmann, Frank Schirrmeister. 286-287 [doi]
- Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applicationsTsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang. 288-289 [doi]
- A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applicationsJyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho. 290-291 [doi]
- Hierarchical power distribution and power management scheme for a single chip mobile processorToshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno. 292-295 [doi]
- Buffer insertion in large circuits with constructive solution search techniquesMandar Waghmode, Zhuo Li, Weiping Shi. 296-301 [doi]
- Low-power repeater insertion with both delay and slew rate constraintsYuantao Peng, Xun Liu. 302-307 [doi]
- Fast algorithms for slew constrained minimum cost buffering308-313 [doi]
- A flexible and scalable methodology for GHz-speed structural testVikram Iyengar, Gary Grise, Mark Taylor. 314-319 [doi]
- Timing-based delay test for screening small delay defectsNisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram. 320-325 [doi]
- Hold time validation on silicon and the relevance of hazards in timing analysisAmitava Majumdar, Wei-Yu Chen, Jun Guo. 326-331 [doi]
- Practical methods in coverage-oriented verification of the merom microprocessorAlon Gluska. 332-337 [doi]
- Verification of the cell broadband engine:::TM::: processorKanna Shimizu, Sanjay Gupta, Tatsuya Koyama, Takashi Omizo, Jamee Abdulhafiz, Larry McConville, Todd Swanson. 338-343 [doi]
- Shielding against design flaws with field repairable control logicIlya Wagner, Valeria Bertacco, Todd M. Austin. 344-347 [doi]
- Scheduling-based test-case generation for verification of multimedia SoCsAmir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen. 348-351 [doi]
- Rapid and low-cost context-switch through embedded processor customization for real-time and control applicationsXiangrong Zhou, Peter Petrov. 352-357 [doi]
- Efficient detection and exploitation of infeasible paths for software timing analysisVivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen. 358-363 [doi]
- Leakage-aware intraprogram voltage scaling for embedded processorsPo-Kuan Huang, Soheil Ghiasi. 364-369 [doi]
- Building a standard ESL design and verification methodology: is it just a dream?Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch. 370-371 [doi]
- CAD challenges for leading-edge multimedia designsAndrew B. Kahng. 372 [doi]
- BoxRouter: a new global router based on box expansion and progressive ILPMinsik Cho, David Z. Pan. 373-378 [doi]
- Steiner network construction for timing critical netsShiyan Hu, Qiuyang Li, Jiang Hu, Peng Li. 379-384 [doi]
- Circuit simulation based obstacle-aware Steiner routingYiyu Shi, Paul Mesa, Hao Yu, Lei He. 385-388 [doi]
- Timing-driven Steiner trees are (practically) freeCharles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang. 389-392 [doi]
- Systematic software-based self-test for pipelined processorsMihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi. 393-398 [doi]
- A test pattern ordering algorithm for diagnosis with truncated fail dataGang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski. 399-404 [doi]
- DFT for controlled-impedance I/O buffersAhmad A. Al-Yamani. 405-410 [doi]
- Variation-aware analysis: savior of the nanometer era?Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic. 411-412 [doi]
- A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOSHari Ananthan, Kaushik Roy. 413-418 [doi]
- A PLA based asynchronous micropipelining approach for subthreshold circuit designNikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri. 419-424 [doi]
- Subthreshold logical effort: a systematic framework for optimal subthreshold device sizingJohn Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim. 425-428 [doi]
- Timing-constrained and voltage-island-aware voltage assignmentHuaizhi Wu, Martin D. F. Wong, I-Min Liu. 429-432 [doi]
- An efficient and versatile scheduling algorithm based on SDC formulationJason Cong, Zhiru Zhang. 433-438 [doi]
- Register binding for clock period minimizationShih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu. 439-444 [doi]
- Towards the automatic exploration of arithmetic-circuit architecturesAjay K. Verma, Paolo Ienne. 445-450 [doi]
- Design space exploration using time and resource duality with the ant colony optimizationGang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner. 451-454 [doi]
- Rapid estimation of control delay from high-level specificationsGagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda. 455-458 [doi]
- Design challenges for next-generation multimedia, game and entertainment platformsJohn M. Cohn, Jeong-Taek Kong, Chris Malachowsky, Rich Tobias, B. Traw. 459 [doi]
- Architecture-aware FPGA placement using metric embeddingPadmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi. 460-465 [doi]
- Efficient SAT-based Boolean matching for FPGA technology mappingSean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan. 466-471 [doi]
- Optimal simultaneous mapping and clustering for FPGA delay optimizationJoey Y. Lin, Deming Chen, Jason Cong. 472-477 [doi]
- Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reductionYu Hu, Yan Lin, Lei He, Tim Tuan. 478-483 [doi]
- VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminalsHiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro. 484-489 [doi]
- A network security processor design based on an integrated SOC design and test platformChen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang. 490-495 [doi]
- Software architecture exploration for high-performance security processing on a multiprocessor mobile SoCDivya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar. 496-501 [doi]
- IMPRES: integrated monitoring for processor reliability and securityRoshan G. Ragel, Sri Parameswaran. 502-505 [doi]
- A parallelized way to provide data encryption and integrity checking on a processor-memory busReouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez. 506-509 [doi]
- Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiabilityJin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske. 510-515 [doi]
- Exploiting K-Distance Signature for Boolean Matching and G-Symmetry DetectionKuo-Hua Wang. 516-521 [doi]
- Gain-based technology mapping for minimum runtime leakage under input vector uncertaintyAshish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky. 522-527 [doi]
- Gate sizing: finFETs vs 32nm bulk MOSFETsBrian Swahn, Soha Hassoun. 528-531 [doi]
- DAG-aware AIG rewriting a fresh look at combinational logic synthesisAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton. 532-535 [doi]
- Energy-scalable OFDM transmitter design and controlBjörn Debaillie, Bruno Bougard, Gregory Lenoir, Gerd Vandersteen, Francky Catthoor. 536-541 [doi]
- Systematic temperature sensor allocation and placement for microprocessorsRajarshi Mukherjee, Seda Ogrenci Memik. 542-547 [doi]
- HybDTM: a coordinated hardware-software approach for dynamic thermal managementAmit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha. 548-553 [doi]
- A systematic method for functional unit power estimation in microprocessorsWei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan. 554-557 [doi]
- Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithmFelix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. 558-561 [doi]
- Extending the lifetime of fuel cell based hybrid systemsJianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula. 562-567 [doi]
- High-level power management of embedded systems with application-specific energy cost functionsYoungjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula. 568-573 [doi]
- Communication latency aware low power NoC synthesisYuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng. 574-579 [doi]
- Optimality study of resource binding with multi-VddsDeming Chen, Jason Cong, Yiping Fan, Junjuan Xu. 580-585 [doi]
- SMERT: energy-efficient design of a multimedia messaging system for mobile devicesLin Zhong, Bin Wei, Michael J. Sinclair. 586-591 [doi]
- Signature-based workload estimation for mobile 3D graphicsBren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu. 592-597 [doi]
- Games are up for DVFSYan Gu, Samarjit Chakraborty, Wei Tsang Ooi. 598-603 [doi]
- Backlight dimming in power-aware mobile displaysAli Iranli, Wonbok Lee, Massoud Pedram. 604-607 [doi]
- Minimization for LED-backlit TFT-LCDsWei-Chung Cheng, Chain-Fu Chao. 608-611 [doi]
- Leakage power reduction of embedded memories on FPGAs through location assignmentYan Meng, Timothy Sherwood, Ryan Kastner. 612-617 [doi]
- A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chipDavid Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias. 618-623 [doi]
- An adaptive FPGA architecture with process variation compensation and reduced leakageGeorges Nabaa, Navid Azizi, Farid N. Najm. 624-629 [doi]
- FLAW: FPGA lifetime awarenessSuresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari. 630-635 [doi]
- Solution-processed infrared photovoltaic devicesDean D. MacNeil, Edward H. Sargent. 636-638 [doi]
- Circuits for energy harvesting sensor signal processingRajeevan Amirtharajah, Justin Wenck, Jamie Collier, Jeff Siebert, Bicky Zhou. 639-644 [doi]
- Systems for human-powered mobile computingJoseph A. Paradiso. 645-650 [doi]
- Harvesting aware power management for sensor networksAman Kansal, Jason Hsu, Mani B. Srivastava, Vijay Raghunathan. 651-656 [doi]
- Synthesis of synchronous elastic architecturesJordi Cortadella, Michael Kishinevsky, Bill Grundmann. 657-662 [doi]
- Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraintSujan Pandey, Manfred Glesner. 663-668 [doi]
- Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programmingLevent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro. 669-674 [doi]
- Behavior and communication co-optimization for systems with sequential communication mediaJason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang. 675-678 [doi]
- Synthesis of high-performance packet processing pipelinesCristian Soviani, Ilija Hadzic, Stephen A. Edwards. 679-682 [doi]
- Buffer memory optimization for video codec application modeled in SimulinkSang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya. 689-694 [doi]
- Configurable cache subsetting for fast cache tuningPablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid. 695-700 [doi]
- High-performance operating system controlled memory compressionLei Yang, Haris Lekatsas, Robert P. Dick. 701-704 [doi]
- A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessorsVladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss. 705-708 [doi]
- Tomorrow s analog: just dead or just different?Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini. 709-710 [doi]
- NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architectureWei Zhang, Niraj K. Jha, Li Shang. 711-716 [doi]
- Modeling and analysis of circuit performance of ballistic CNFETBipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee. 717-722 [doi]
- Topology aware mapping of logic functions onto nanowire-based crossbar architecturesWenjing Rao, Alex Orailoglu, Ramesh Karri. 723-726 [doi]
- A new hybrid FPGA with nanoscale clusters and CMOS routingReza M. Rad, Mohammad Tehranipoor. 727-730 [doi]
- Directed-simulation assisted formal verification of serial protocol and bridgeSaurav Gorai, Saptarshi Biswas, Lovleen Bhatia, Praveen Tiwari, Raj S. Mitra. 731-736 [doi]
- Guiding simulation with increasingly refined abstract tracesKuntal Nanshi, Fabio Somenzi. 737-742 [doi]
- Mining global constraints for improving bounded sequential equivalence checkingWeixin Wu, Michael S. Hsiao. 743-748 [doi]
- An IC manufacturing yield model considering intra-die variationsJianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang. 749-754 [doi]
- Novel full-chip gridless routing considering double-via insertionHuang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han. 755-760 [doi]
- Optimal jumper insertion for antenna avoidance under ratio upper-boundJia Wang, Hai Zhou. 761-766 [doi]
- MARS-C: modeling and reduction of soft errors in combinational circuitsNatasa Miskov-Zivanov, Diana Marculescu. 767-772 [doi]
- A design approach for radiation-hard digital electronicsRajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi. 773-778 [doi]
- A family of cells to reduce the soft-error-rate in ternary-CAMNavid Azizi, Farid N. Najm. 779-784 [doi]
- Process variation aware OPC with variational lithography modelingPeng Yu, Sean X. Shi, David Z. Pan. 785-790 [doi]
- Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuitsSarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao. 791-796 [doi]
- Computation of accurate interconnect process parameter values for performance corners under process variationsFrank Huebbers, Ali Dasdan, Yehea I. Ismail. 797-800 [doi]
- Standard cell characterization considering lithography induced variationsKe Cao, Sorin Dobre, Jiang Hu. 801-804 [doi]
- Building a verification test plan: trading brute force for finesseJ. Bergeron, H. Foster, A. Piziali, R. S. Mitra, C. Ahlschlager, D. Stein. 805-806 [doi]
- Electronics beyond nano-scale CMOSShekhar Borkar. 807-808 [doi]
- Are carbon nanotubes the future of VLSI interconnections?Kaustav Banerjee, Navin Srivastava. 809-814 [doi]
- The zen of nonvolatile memoriesErwin J. Prinz. 815-820 [doi]
- Formal analysis of hardware requirementsIngo Pill, Simone Semprini, Roberto Cavada, Marco Roveri, Roderick Bloem, Alessandro Cimatti. 821-826 [doi]
- Test generation games from formal specificationsAnsuman Banerjee, Bhaskar Pal, Sayantan Das, Abhijeet Kumar, Pallab Dasgupta. 827-832 [doi]
- Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systemsLap-Fai Leung, Chi-Ying Tsui. 833-838 [doi]
- Prediction-based flow control for network-on-chip trafficÜmit Y. Ogras, Radu Marculescu. 839-844 [doi]
- A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chipSrinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli. 845-848 [doi]
- DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chipMing Li, Qing-An Zeng, Wen-Ben Jone. 849-852 [doi]
- The importance of adopting a package-aware chip design flowKaushik Sheth, Egino Sarto, Joel McGrath. 853-856 [doi]
- Silicon carrier for computer systemsChirag S. Patel. 857-862 [doi]
- Optimizing code parallelization through a constraint network based approachOzcan Ozturk, Guilin Chen, Mahmut T. Kandemir. 863-688 [doi]
- 4.25 Gb/s laser driver: design challenges and EDA tool limitationsBenjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann. 863-866 [doi]
- Power-centric design of high-speed I/OsHamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang. 867-872 [doi]
- A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBWPierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni. 873-878 [doi]
- SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiersArthur Nieuwoudt, Tamer Ragheb, Yehia Massoud. 879-884 [doi]
- Chameleon ART: a non-optimization based analog design migration frameworkSherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein. 885-888 [doi]
- Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISPMichaël Goffioul, Gerd Vandersteen, Joris Van Driessche, Björn Debaillie, Boris Come. 889-892 [doi]
- Efficient simulation of critical synchronous dataflow graphsChia-Jui Hsu, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, Shuvra S. Bhattacharyya. 893-898 [doi]
- Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphsSander Stuijk, Marc Geilen, Twan Basten. 899-904 [doi]
- GreenBus: a generic interconnect fabric for transaction level modellingWolfgang Klingauf, Robert Günzel, Oliver Bringmann, Pavel Parfuntseu, Mark Burton. 905-910 [doi]
- A framework for embedded system specification under different models of computation in SystemCFernando Herrera, Eugenio Villar. 911-914 [doi]
- A model-driven design environment for embedded systemsElvinia Riccobene, Patrizia Scandurra, Alberto Rosti, Sara Bocchio. 915-918 [doi]
- Design automation for DNA self-assembled nanostructuresConstantin Pistol, Alvin R. Lebeck, Chris Dwyer. 919-924 [doi]
- Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*William L. Hwang, Fei Su, Krishnendu Chakrabarty. 925-930 [doi]
- Placement of digital microfluidic biochips using the t-tree formulationPing-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang. 931-934 [doi]
- A high density, carbon nanotube capacitor for decoupling applicationsMark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy. 935-938 [doi]
- State encoding of large asynchronous controllersJosep Carmona, Jordi Cortadella. 939-944 [doi]
- An efficient retiming algorithm under setup and hold constraintsChuan Lin, Hai Zhou. 945-950 [doi]
- ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew schedulingKui Wang, Lian Duan, Xu Cheng. 951-954 [doi]
- Budgeting-free hierarchical design method for large scale and high-performance LSIsYuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa. 955-958 [doi]
- Variability driven gate sizing for binning yield optimizationAzadeh Davoodi, Ankur Srivastava. 959-964 [doi]
- Elmore model for energy estimation in RC treesQuming Zhou, Kartik Mohanram. 965-970 [doi]
- Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAMSwaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy. 971-976 [doi]
- A novel variation-aware low-power keeper architecture for wide fan-in dynamic gatesHamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee. 977-982 [doi]
- Standard cell library optimization for leakage reductionSaumil Shah, Puneet Gupta, Andrew B. Kahng. 983-986 [doi]
- Low-power bus encoding using an adaptive hybrid algorithmAvnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu. 987-990 [doi]
- A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchyGian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee. 991-996 [doi]
- Exploring compromises among timing, power and temperature in three-dimensional integrated circuitsHao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis. 997-1002 [doi]
- Efficient escape routing for hexagonal array of high density I/OsRui Shi, Chung-Kuan Cheng. 1003-1008 [doi]
- System level signal and power integrity analysis methodology for system-in-package applicationsRohan Mandrekar, Krishna Bharath, Krishna Srinivasan, Ege Engin, Madhavan Swaminathan. 1009-1012 [doi]
- PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitationsWm. Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel. 1013-1016 [doi]
- A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillatorsXiaolue Lai, Jaijeet S. Roychowdhury. 1017-1022 [doi]
- Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decouplingYing Wei, Alex Doboli. 1023-1028 [doi]
- A robust envelope following method applicable to both non-autonomous and oscillatory circuitsTing Mei, Jaijeet S. Roychowdhury. 1029-1034 [doi]
- Lookup table based simulation and statistical modeling of Sigma-Delta ADCsGuo Yu, Peng Li. 1035-1040 [doi]
- Clock buffer and wire sizing using sequential programmingMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown. 1041-1046 [doi]
- Modeling and minimization of PMOS NBTI effect for robust nanometer designRakesh Vattikonda, Wenping Wang, Yu Cao. 1047-1052 [doi]
- A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structuresChuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala. 1053-1056 [doi]
- Reliability modeling and management in dynamic microprocessor-based systemsEric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge. 1057-1060 [doi]
- DFM: where s the proof of value?Shishpal Rawat, Raul Camposano, A. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, A. Sharan. 1061-1062 [doi]
- Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verificationXiushan Feng, Alan J. Hu. 1063-1068 [doi]
- Transistor abstraction for the functional verification of FPGAsGuy Dupenloup, Thierry Lemeunier, Roland Mayr. 1069-1072 [doi]
- Automatic invariant strengthening to prove properties in bounded model checkingMohammad Awedh, Fabio Somenzi. 1073-1076 [doi]
- Fast falsification based on symbolic bounded property checkingPrakash Mohan Peranandam, Pradeep Kumar Nalla, Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wolfgang Rosenstiel. 1077-1082 [doi]
- Unknown-tolerance analysis and test-quality control for test response compaction using space compactorsMango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei. 1083-1088 [doi]
- Test response compactor with programmable selectorGrzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. 1089-1094 [doi]
- Fault detection and diagnosis with parity trees for space compaction of test responsesHarald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke. 1095-1098 [doi]
- Multiple-detect ATPG based on physical neighborhoodsJeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton. 1099-1102 [doi]
- Constraint-driven floorplan repairMichael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack. 1103-1108 [doi]
- Optimal cell flipping in placement and floorplanningChiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu. 1109-1114 [doi]
- A new LP based incremental timing driven placement for high performance designsTao Luo, David Newmark, David Z. Pan. 1115-1120 [doi]