Table of Contents

• Mapping on multi/many-core systems: survey of current and emerging trendsAmit Kumar Singh, Muhammad Shafique, Akash Kumar, Jörg Henkel. 1 [doi]
• Workload and user experience-aware dynamic reliability management in multicore processorsPietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini. 2 [doi]
• Liveness evaluation of a cyclo-static DataFlow graphMohamed Benazouz, Alix Munier Kordon, Thomas Hujsa, Bruno Bodin. 3 [doi]
• Double patterning lithography-aware analog placementHsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang. 4 [doi]
• Simultaneous analog placement and routing with current flow and current density considerationsHung-Chih Ou, Hsing-Chih Chang Chien, Yao-Wen Chang. 5 [doi]
• Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuitsKuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao. 6 [doi]
• Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engineBeiye Liu, Miao Hu, Hai Li, Zhi-Hong Mao, Yiran Chen, Tingwen Huang, Wei Zhang. 7 [doi]
• Dynamic behavior of cell signaling networks: model design and analysis automationNatasa Miskov-Zivanov, Diana Marculescu, James R. Faeder. 8 [doi]
• Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidanceJason Cong, Bingjun Xiao. 9 [doi]
• An efficient and effective analytical placer for FPGAsTzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang. 10 [doi]
• Throughput-oriented kernel porting onto FPGAsAlexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, Jason Cong, Yun Liang. 11 [doi]
• Memory partitioning for multidimensional arrays in high-level synthesisYuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong. 12 [doi]
• Balancing security and utility in medical devices?Masoud Rostami, Wayne Burleson, Farinaz Koushanfar, Ari Juels. 13 [doi]
• Towards trustworthy medical devices and body area networksMeng Zhang, Anand Raghunathan, Niraj K. Jha. 14 [doi]
• Low-energy encryption for medical devices: security adds an extra design dimensionJunfeng Fan, Oscar Reparaz, Vladimir Rozic, Ingrid Verbauwhede. 15 [doi]
• Aging-aware compiler-directed VLIW assignment for GPGPU architecturesAbbas Rahimi, Luca Benini, Rajesh K. Gupta. 16 [doi]
• Exploiting program-level masking and error propagation for constrained reliability optimizationMuhammad Shafique, Semeen Rehman, Pau Vilimelis Aceituno, Jörg Henkel. 17 [doi]
• REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula. 18 [doi]
• Polyhedral model based mapping optimization of loop nests for CGRAsDajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei. 19 [doi]
• reciprocative error compensationLingamneni Avinash, Arindam Basu, Christian C. Enz, Krishna V. Palem, Christian Piguet. 20 [doi]
• Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture descriptionHarry Wagstaff, Miles Gould, Björn Franke, Nigel P. Topham. 21 [doi]
• XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMsSu Myat Min, Haris Javaid, Sri Parameswaran. 22 [doi]
• Towards variation-aware system-level power estimation of DRAMs: an empirical approachKarthik Chandrasekar 0001, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens. 23 [doi]
• TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodesArindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest. 24 [doi]
• Stitch-aware routing for multiple e-beam lithographyShao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang. 25 [doi]
• Automatic design rule correction in presence of multiple grids and track patternsNitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. 26 [doi]
• Multiple chip planning for chip-interposer codesignYuan-Kai Ho, Yao-Wen Chang. 27 [doi]
• GPU-based n-detect transition fault ATPGKuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li. 28 [doi]
• Post-silicon conformance checking with virtual prototypesLi Lei, Fei Xie, Kai Cong. 29 [doi]
• On testing timing-speculative circuitsFeng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu. 30 [doi]
• An ATE assisted DFD technique for volume diagnosis of scan chainsSubhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur. 31 [doi]
• Predicting future technology performanceAsen Asenov, Craig Alexander, Craig Riddet, Ewan Towie. 32 [doi]
• Predicting future product performance: modeling and evaluation of standard cells in FinFET technologiesVeit Kleeberger, Helmut E. Graeb, Ulf Schlichtmann. 33 [doi]
• The ITRS design technology and system drivers roadmap: process and statusAndrew B. Kahng. 34 [doi]
• Proactive circuit allocation in multiplane NoCsAhmed Abousamra, Alex K. Jones, Rami G. Melhem. 35 [doi]
• A heterogeneous multiple network-on-chip design: an application-aware approachAsit K. Mishra, Onur Mutlu, Chita R. Das. 36 [doi]
• Designing energy-efficient NoC for real-time embedded systems through slack optimizationJia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie. 37 [doi]
• RISO: relaxed network-on-chip isolation for cloud processorsHang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li 0001. 38 [doi]
• Smart hill climbing for agile dynamic mapping in many-core systemsMohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila. 39 [doi]
• HCI-tolerant NoC router microarchitectureDean Michael Ancajas, James McCabe Nickerson, Koushik Chakraborty, Sanghamitra Roy. 40 [doi]
• Optimization of quantum circuits for interaction distance in linear nearest neighbor architecturesAlireza Shafaei, Mehdi Saeedi, Massoud Pedram. 41 [doi]
• LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabricMohammad Javad Dousti, Massoud Pedram. 42 [doi]
• Pareto epsilon-dominance and identifiable solutions for BioCAD modelingClaudio Angione, Jole Costanza, Giovanni Carapezza, Pietro Liò, Giuseppe Nicosia. 43 [doi]
• Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operationsYan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho. 44 [doi]
• Gene modification identification under flux capacity uncertaintyMona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun. 45 [doi]
• A field-programmable pin-constrained digital microfluidic biochipDaniel Grissom, Philip Brisk. 46 [doi]
• BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decompositionLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 47 [doi]
• Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structuresSubhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan. 48 [doi]
• Synthesis of feedback decoders for initialized encodersKuan-Hua Tu, Jie-Hong R. Jiang. 49 [doi]
• On learning-based methods for design-space exploration with high-level synthesisHung-Yi Liu, Luca P. Carloni. 50 [doi]
• Runtime dependency analysis for loop pipelining in high-level synthesisMythri Alle, Antoine Morvan, Steven Derrien. 51 [doi]
• A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devicesAlessandro Antonio Nacci, Vincenzo Rana, Francesco Bruschi, Donatella Sciuto, Ivan Beretta, David Atienza. 52 [doi]
• Cross-layer racetrack memory design for ultra high density and low power consumptionZhenyu Sun, Wenqing Wu, Hai Helen Li. 53 [doi]
• Improving the energy efficiency of hardware-assisted watchpoint systemsVasileios Karakostas, Sasa Tomic, Osman S. Unsal, Mario Nemirovsky, Adrián Cristal. 54 [doi]
• Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networksNaoya Onizawa, Warren J. Gross. 55 [doi]
• Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraintsDebashis Banerjee, Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee. 56 [doi]
• Improving charging efficiency with workload scheduling in energy harvesting embedded systemsYukan Zhang, Yang Ge, Qinru Qiu. 57 [doi]
• Creation of ESL power models for communication architectures using automatic calibrationStefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang. 58 [doi]
• A transmission gate physical unclonable function and on-chip voltage-to-digital conversion techniqueRaj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic. 59 [doi]
• RESP: a robust physical unclonable function retrofitted into embedded SRAM arrayYu Zheng, Maryamsadat Hashemian, Swarup Bhunia. 60 [doi]
• VeriTrust: verification for hardware trustJie Zhang, Feng Yuan, Lingxiao Wei, Zelong Sun, Qiang Xu. 61 [doi]
• RASTER: runtime adaptive spatial/temporal error resiliency for embedded processorsTuo Li 0001, Muhammad Shafique, Jude Angelo Ambrose, Semeen Rehman, Jörg Henkel, Sri Parameswaran. 62 [doi]
• ABCD-L: approximating continuous linear systems using boolean modelsKarthik V. Aadithya, Jaijeet S. Roychowdhury. 63 [doi]
• Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage dataFa Wang, Wangyang Zhang, Shupeng Sun, Xin Li, Chenjie Gu. 64 [doi]
• Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validationChenjie Gu, Eli Chiprout, Xin Li. 65 [doi]
• Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysisHonghuang Lin, Peng Li, Chris J. Myers. 66 [doi]
• Machine-learning-based hotspot detection using topological classification and critical feature extractionYen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles Chiang. 67 [doi]
• A novel fuzzy matching model for lithography hotspot detectionSheng-Yuan Lin, Jing-Yi Chen, Jin-Cheng Li, Wan-yu Wen, Shih-Chieh Chang. 68 [doi]
• An efficient layout decomposition approach for triple patterning lithographyJian Kuang, Evangeline F. Y. Young. 69 [doi]
• E-BLOW: e-beam lithography overlapping aware stencil planning for MCC systemBei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan. 70 [doi]
• Automatic clustering of wafer spatial signaturesWangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar. 71 [doi]
• Multidimensional analog test metrics estimation using extreme value theory and statistical blockadeHaralampos-G. D. Stratigopoulos, Pierre Faubet, Yoann Courant, Firas Mohamed. 72 [doi]
• High-throughput TSV testing and characterization for 3D integration using thermal mappingKapil Dev, Gary Woods, Sherief Reda. 73 [doi]
• On effective and efficient in-field TSV repair for stacked 3D ICsLi Jiang, Fangming Ye, Qiang Xu, Krishnendu Chakrabarty, Bill Eklow. 74 [doi]
• Cloud platforms and embedded computing: the operating systems of the futureJan S. Rellermeyer, Seong-Won Lee, Michael Kistler. 75 [doi]
• Tessellation: refactoring the OS around explicit resource containers with continuous adaptationJuan A. Colmenares, Gage Eads, Steven A. Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, Davide B. Bartolini, Nitesh Mor, Krste Asanovic, John Kubiatowicz. 76 [doi]
• The autonomic operating system research project: achievements and future directionsDavide B. Bartolini, Riccardo Cattaneo, Gianluca Durelli, Martina Maggio, Marco D. Santambrogio, Filippo Sironi. 77 [doi]
• Role of power grid in side channel attack and power-grid-aware secure designXinmu Wang, Wen Yueh, Debapriya Basu Roy, Seetharam Narasimhan, Yu Zheng, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, Swarup Bhunia. 78 [doi]
• NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance countersXueyang Wang, Ramesh Karri. 79 [doi]
• High-performance hardware monitors to protect network processors from data plane attacksHarikrishnan Chandrikakutty, Deepak Unnikrishnan, Russell Tessier, Tilman Wolf. 80 [doi]
• Compiler-based side channel vulnerability analysis and optimized countermeasures applicationGiovanni Agosta, Alessandro Barenghi, Massimo Maggi, Gerardo Pelosi. 81 [doi]
• Lighting the dark silicon by exploiting heterogeneity on future processorsYing Zhang, Lu Peng, Xin Fu, Yue Hu. 82 [doi]
• Simultaneous multithreading support in embedded distributed memory MPSoCsRafael Garibotti, Luciano Ost, Rémi Busseuil, Mamady kourouma, Chris Adeniyi-Jones, Gilles Sassatelli, Michel Robert. 83 [doi]
• APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operationBojan Maric, Jaume Abella, Mateo Valero. 84 [doi]
• An optimized page translation for mobile virtualizationYuan-Cheng Lee, Chih-wen Hsueh. 85 [doi]
• Scalable vectorless power grid current integrity verificationZhuo Feng. 86 [doi]
• Constraint abstraction for vectorless power grid verificationXuanxing Xiong, Jia Wang. 87 [doi]
• The impact of electromigration in copper interconnects on power grid integrityVivek Mishra, Sachin S. Sapatnekar. 88 [doi]
• TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulationsLengfei Han, Xueqian Zhao, Zhuo Feng. 89 [doi]
• An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problemJuyeon Kim, Deokjin Joo, Taewhan Kim. 90 [doi]
• Smart non-default routing for clock power reductionAndrew B. Kahng, Seokhyeong Kang, Hyein Lee. 91 [doi]
• Routing congestion estimation with real design constraintsWen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan. 92 [doi]
• Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithographyYuelin Du, Qiang Ma 0002, Hua Song, James Shiely, Gerard Luk-Pat, Alexander Miloslavsky, Martin D. F. Wong. 93 [doi]
• 21st century digital design toolsWilliam J. Dally, Chris Malachowsky, Stephen W. Keckler. 94 [doi]
• System architecture and software design for electric vehiclesMartin Lukasiewycz, Sebastian Steinhorst, Sidharta Andalam, Florian Sagstetter, Peter Waszecki, Wanli Chang, Matthias Kauer, Philipp Mundhenk, Shanker Shreejith, Suhaib A. Fahmy, Samarjit Chakraborty. 95 [doi]
• Model-based development and verification of control software for electric vehiclesDip Goswami, Martin Lukasiewycz, Matthias Kauer, Sebastian Steinhorst, Alejandro Masrur, Samarjit Chakraborty, S. Ramesh. 96 [doi]
• Hybrid energy storage systems and battery management for electric vehiclesSangyoung Park, Younghyun Kim, Naehyuck Chang. 97 [doi]
• Reliability challenges for electric vehicles: from devices to architecture and systems softwareGeorg Georgakos, Ulf Schlichtmann, Reinhard Schneider 0001, Samarjit Chakraborty. 98 [doi]
• Reliable on-chip systems in the nano-era: lessons learnt and future trendsJörg Henkel, Lars Bauer, Nikil Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn. 99 [doi]
• A layout-based approach for multiple event transient analysisMojtaba Ebrahimi, Hossein Asadi, Mehdi Baradaran Tahoori. 100 [doi]
• Quantitative evaluation of soft error injection techniques for robust system designHyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra. 101 [doi]
• Efficiently tolerating timing violations in pipelined microprocessorsKoushik Chakraborty, Brennan Cozzens, Sanghamitra Roy, Dean Michael Ancajas. 102 [doi]
• Hierarchical decoding of double error correcting codes for high speed reliable memoriesZhen Wang. 103 [doi]
• Power benefit study for ultra-high density transistor-level monolithic 3D ICsYoung-Joon Lee, Daniel B. Limbrick, Sung Kyu Lim. 104 [doi]
• Rapid exploration of processing and design guidelines to overcome carbon nanotube variationsGage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra. 105 [doi]
• Minimum-energy state guided physical design for nanomagnet logicShiliang Liu, György Csaba, Xiaobo Sharon Hu, Edit Varga, Michael T. Niemier, Gary H. Bernstein, Wolfgang Porod. 106 [doi]
• Ultra low power associative computing with spin neurons and resistive crossbar memoryMrigank Sharad, Deliang Fan, Kaushik Roy. 107 [doi]
• Understanding the trade-offs in multi-level cell ReRAM memory designCong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie. 108 [doi]
• Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifierAmit Ranjan Trivedi, Sergio Carlo, Saibal Mukhopadhyay. 109 [doi]
• Energy-optimal SRAM supply voltage scheduling under lifetime and error constraintsAndrea Calimera, Enrico Macii, Massimo Poncino. 110 [doi]
• Relax-and-retime: a methodology for energy-efficient recovery based designShankar Ganesh Ramasubramanian, Swagath Venkataramani, Adithya Parandhaman, Anand Raghunathan. 111 [doi]
• Post-placement voltage island generation for timing-speculative circuitsRong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu. 112 [doi]
• Analysis and characterization of inherent application resilience for approximate computingVinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan. 113 [doi]
• Dynamic voltage and frequency scaling for shared resources in multicore processor designsXi Chen, Zheng Xu, HyungJun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras, Raid Zuhair Ayoub. 114 [doi]
• Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systemsAmit Kumar Singh, Anup Das, Akash Kumar. 115 [doi]
• Verifying SystemC using an intermediate verification language and symbolic simulationHoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler. 116 [doi]
• Handling design and implementation optimizations in equivalence checking for behavioral synthesisZhenkun Yang, Sandip Ray, Kecheng Hao, Fei Xie. 117 [doi]
• A counterexample-guided interpolant generation algorithm for SAT-based model checkingCheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang. 118 [doi]
• A robust constraint solving framework for multiple constraint sets in constrained random verificationBo-Han Wu, Chung-Yang (Ric) Huang. 119 [doi]
• Simulation knowledge extraction and reuse in constrained random processor verificationWen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir. 120 [doi]
• Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validationAdam B. Kinsman, Ho Fai Ko, Nicola Nicolici. 121 [doi]
• The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputersJ. P. Grossman, Brian Towles, Joseph A. Bank, David E. Shaw. 122 [doi]
• Towards structured ASICs using polarity-tunable Si nanowire transistorsPierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli. 123 [doi]
• Sacha: the Stanford carbon nanotube controlled handshaking robotMax M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra. 124 [doi]
• Electrical artificial skin using ultraflexible organic transistorTsuyoshi Sekitani, Tomoyuki Yokota, Makoto Takamiya, Takayasu Sakurai, Takao Someya. 125 [doi]
• Non-volatile FPGAs based on spintronic devicesOlivier Goncalves, Guillaume Prenat, Gregory di Pendina, Bernard Dieny. 126 [doi]
• Relays do not leak: CMOS doesHossein Fariborzi, Fred Chen, Rhesa Nathanael, I.-Ru Chen, Louis Hutin, Rinus Lee, Tsu-Jae King Liu, Vladimir Stojanovic. 127 [doi]
• Single-photon image sensorsEdoardo Charbon, Francesco Regazzoni. 128 [doi]
• A novel analytical method for worst case response time estimation of distributed embedded systemsJinwoo Kim, Hyunok Oh, Junchul Choi, Hyojin Ha, Soonhoi Ha. 129 [doi]
• Optimizations for configuring and mapping software pipelines in many core systemsJanmartin Jahn, Santiago Pagani, Sebastian Kobbe, Jian-Jia Chen, Jörg Henkel. 130 [doi]
• A scenario-based run-time task mapping algorithm for MPSoCsWei Quan, Andy D. Pimentel. 131 [doi]
• Early exploration for platform architecture instantiation with multi-mode application partitioningPrashant Agrawal, Praveen Raghavan, Matthias Hartmann, Namita Sharma, Liesbet Van der Perre, Francky Catthoor. 132 [doi]
• CoARX: a coprocessor for ARX-based cryptographic algorithmsKhawar Shahzad, Ayesha Khalid, Zoltán Endre Rákossy, Goutam Paul, Anupam Chattopadhyay. 133 [doi]
• Reconfigurable pipelined coprocessor for multi-mode communication transmissionLiang Tang, Jude Angelo Ambrose, Sri Parameswaran. 134 [doi]
• Accelerators for biologically-inspired attention and recognitionMi Sun Park, Chuanjun Zhang, Michael DeBole, Srinidhi Kestur. 135 [doi]
• Stochastic circuits for real-time image-processing applicationsArmin Alaghi, Cheng Li, John P. Hayes. 136 [doi]
• An event-driven simulation methodology for integrated switching power supplies in SystemVerilogJi-Eun Jang, Myeong-Jae Park, Jaeha Kim. 137 [doi]
• A new time-stepping method for circuit simulationG. Peter Fang. 138 [doi]
• Time-domain segmentation based massively parallel simulation for ADCsZuochang Ye, Bichen Wu, Song Han, Yang Li. 139 [doi]
• A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectricsBangda Zhou, Haixin Liu, Dan Jiao. 140 [doi]
• FPGA code accelerators - the compiler perspectiveWalid A. Najjar, Jason R. Villarreal. 141 [doi]
• Can CAD cure cancer?Smita Krishnaswamy, Bernd Bodenmiller, Dana Pe'er. 142 [doi]
• Let's put the car in your phone!Martin Geier, Martin Becker 0001, Daniel Yunge, Benedikt Dietrich, Reinhard Schneider 0001, Dip Goswami, Samarjit Chakraborty. 143 [doi]
• The undetectable and unprovable hardware trojan horseSheng Wei, Miodrag Potkonjak. 144 [doi]
• Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of powerSwaroop Ghosh. 145 [doi]
• Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetchingEmilio Wuerges, Rômulo Silva de Oliveira, Luiz C. V. dos Santos. 146 [doi]
• Integrated instruction cache analysis and locking in multitasking real-time systemsHuping Ding, Yun Liang, Tulika Mitra. 147 [doi]
• Precise timing analysis for direct-mapped cachesSidharta Andalam, Alain Girault, Roopak Sinha, Partha S. Roop, Jan Reineke. 148 [doi]
• SSDM: smart stack data management for software managed multicores (SMMs)Jing Lu, Ke Bai, Aviral Shrivastava. 149 [doi]
• Taming the complexity of coordinated place and routeJin Hu, Myung-Chul Kim, Igor L. Markov. 150 [doi]
• Routability-driven placement for hierarchical mixed-size circuit designsMeng-Kai Hsu, Yi Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang. 151 [doi]
• Ripple 2.0: high quality routability-driven placement via global router integrationXu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka Chun Lam, Wenzan Cai, Evangeline F. Y. Young. 152 [doi]
• Optimization of placement solutions for routabilityWen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li. 153 [doi]
• Exploration with upgradeable models using statistical methods for physical model emulationBailey Miller, Frank Vahid, Tony Givargis. 154 [doi]
• Modular system-level architecture for concurrent cell balancingMatthias Kauer, Swaminathan Naranayaswami, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Lars Hedrich. 155 [doi]
• A method to abstract RTL IP blocks into C++ code and enable high-level synthesisNicola Bombieri, Hung-Yi Liu, Franco Fummi, Luca P. Carloni. 156 [doi]
• DMR3D: dynamic memory relocation in 3D multicore systemsDean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy. 157 [doi]
• Power gating applied to MP-SoCs for standby-mode power managementDavid Flynn. 158 [doi]
• Power management and delivery for high-performance microprocessorsTanay Karnik, Mondira (Mandy) Pant, Shekhar Borkar. 159 [doi]
• Flexible on-chip power delivery for energy efficient heterogeneous systemsBenton H. Calhoun, Kyle Craig. 160 [doi]
• Power and signal integrity challenges in 3D systemsMiguel Corbalan, Anup Keval, Thomas Toms, Durodami Lisk, Riko Radojcic, Matt Nowak. 161 [doi]
• Underpowering NAND flash: profits and perilsHung-Wei Tseng, Laura M. Grupp, Steven Swanson. 162 [doi]
• New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devicesMing-Chang Yang, Yuan-Hao Chang, Che-Wei Tsao, Po-Chun Huang. 163 [doi]
• SAW: system-assisted wear leveling on the write endurance of NAND flash devicesChundong Wang, Weng-Fai Wong. 164 [doi]
• Performance enhancement of garbage collection for flash storage devices: an efficient victim block selection designChe-Wei Tsao, Yuan-Hao Chang, Ming-Chang Yang. 165 [doi]
• DuraCache: a durable SSD cache using MLC NAND flashRen-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen. 166 [doi]
• Distributed stable states for process networks: algorithm, analysis, and experiments on intel SCCDevendra Rai, Lars Schor, Nikolay Stoimenov, Lothar Thiele. 167 [doi]
• Distributed run-time resource management for malleable applications on many-core platformsIraklis Anagnostopoulos, Vasileios Tsoutsouras, Alexandros Bartzas, Dimitrios Soudris. 168 [doi]
• netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systemsYoungHoon Jung, Jinhyung Park, Michele Petracca, Luca P. Carloni. 169 [doi]
• Exploiting just-enough parallelism when mapping streaming applications in hard real-time systemsJiali Teddy Zhai, Mohamed Bamakhrama, Todor Stefanov. 170 [doi]
• On robust task-accurate performance estimationYang Xu, Bo Wang 0010, Ralph Hasholzner, Rafael Rosales, Jürgen Teich. 171 [doi]
• Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errorsPhilip Axer, Rolf Ernst. 172 [doi]
• HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processorsYatish Turakhia, Bharathwaj Raghunathan, Siddharth Garg, Diana Marculescu. 173 [doi]
• Hierarchical power management for asymmetric multi-core in dark silicon eraThannirmalai Somu Muthukaruppan, Mihai Pricopi, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin. 174 [doi]
• Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessorSai Manoj Pudukotai Dinakarrao, Kanwen Wang, Hao Yu. 175 [doi]
• Techniques for energy-efficient power budgeting in data centersXin Zhan, Sherief Reda. 176 [doi]
• Temperature aware thread block scheduling in GPGPUsRajib Nath, Raid Zuhair Ayoub, Tajana Simunic Rosing. 177 [doi]
• VAWOM: temperature and process variation aware wearout management in 3D multicore architectureHossein Tajik, Houman Homayoun, Nikil Dutt. 178 [doi]
• On the potential of 3D integration of inductive DC-DC converter for high-performance power deliverySergio Carlo, Wen Yueh, Saibal Mukhopadhyay. 179 [doi]
• Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICsTaigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim. 180 [doi]
• An accurate semi-analytical framework for full-chip TSV-induced stress modelingYang Li, David Z. Pan. 181 [doi]
• Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimizationVimitha Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan. 182 [doi]
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