Table of Contents

• A systemc TLM framework for distributed simulation of complex systems with unpredictable communicationJulien Peeters, Nicolas Ventroux, Tanguy Sassolas, Lionel Lacassagne. 12-19 [doi]
• Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approachTakieddine Majdoub, Sébastien LeNours, Olivier Pasquier, Fabienne Nouvel. 20-26 [doi]
• Morpheo: A high-performance processor generator for a FPGA implementationMathieu Rosiere, Jean Lou Desbarbieux, Nathalie Drach, Franck Wajsbürt. 27-34 [doi]
• Design of a processor optimized for syntax parsing in video decodersNicolas Siret, Jean-François Nezan, Aimad Rhatay. 35-43 [doi]
• Fast and accurate hybrid power estimation methodology for embedded systemsSanthosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser. 45-51 [doi]
• Embedded operating systems energy overheadBassem Ouni, Cécile Belleudy, Sebastien Bilavarn, Eric Senn. 52-57 [doi]
• Flexible VLIW processor based on FPGA for real-time image processingVincent Brost, Charles Meunier, Debyo Saptono, Fan Yang. 59-66 [doi]
• Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computingMatthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker. 67-74 [doi]
• Task model and online operating system API for hardware tasks in OLLAF platformSamuel Garcia, Bertrand Granado. 75-81 [doi]
• DFG implementation on multi GPU cluster with computation-communication overlapSylvain Huet, Vincent Boulos, Vincent Fristot, Luc Salvo. 83-90 [doi]
• An efficient parallel motion estimation algorithm and X264 parallelization in CUDAYoungsub Ko, Youngmin Yi, Soonhoi Ha. 91-98 [doi]
• Middleware approaches for adaptivity of Kahn Process Networks on Networks-on-ChipEmanuele Cannella, Onur Derin, Todor Stefanov. 100-107 [doi]
• FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case studyManel Hentati, Yassine Aoudni, Jean-François Nezan, Mohamed Abid, Olivier Déforges. 108-114 [doi]
• Graphic rendering application profiling on a shared memory MPSOC architectureMatthieu Texier, Raphaël David, Karim Ben Chehida, Olivier Sentieys. 115-121 [doi]
• High speed VLSI architecture for 2-D lifting Discrete Wavelet TransformAnand D. Darji, Rajul Bansal, S. N. Merchant, Arun N. Chandorkar. 123-128 [doi]
• Pilot studies of wireless sensor networks: Practical experiencesTeemu Laukkarinen, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen. 129-136 [doi]
• Efficient maximal convex custom instruction enumeration for extensible processorsChenglong Xiao, Emmanuel Casseau. 137-143 [doi]
• Efficient FFT pruning algorithm for non-contiguous OFDM systemsRoberto Airoldi, Fabio Garzia, Jari Nurmi. 144-149 [doi]
• Designing processors using MAsS, a modular and lightweight instruction-level exploration toolMatthieu Texier, Erwan Piriou, Mathieu Thevenin, Raphaël David. 150-155 [doi]
• A new approach to 3D form recognition within video capsule endoscopicJade Ayoub, Bertrand Granado, Olivier Romain, Yasser Mohanna. 157-163 [doi]
• A SystemC AMS/TLM platform for CMOS video sensorsFabio Cenni, Serge Scotti, Emmanuel Simeu. 164-169 [doi]
• Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platformsGhislain Roquier, Endri Bezati, Richard Thavot, Marco Mattavelli. 171-177 [doi]
• The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composerFrancesca Palumbo, Nicola Carta, Luigi Raffo. 178-185 [doi]
• A unified hardware/software co-synthesis solution for signal processing systemsEndri Bezati, Hervé Yviquel, Mickaël Raulet, Marco Mattavelli. 186-191 [doi]
• Optimization methodologies for complex FPGA-based signal processing systems with CALAb Al Hadi Ab Rahman, Hossam Amer, Anatoly Prihozhy, Christophe Lucarz, Marco Mattavelli. 192-199 [doi]
• Development of a method for image-based motion estimation of a VTOL-MAV on FPGANatalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker. 201-208 [doi]
• Real-time moving object detection for video surveillance system in FPGATomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon. 209-216 [doi]
• An approach to self-learning multicore reconfiguration management applied on Robotic VisionWalter Stechele, Jan Hartmann, Erik Maehle. 217-222 [doi]
• Power consumption improvement with residue code for fault tolerance on SRAM FPGAFrederic Amiel, Thomas Ea, Vashishtha Vinay. 223-228 [doi]
• Embedded systems security: An evaluation methodology against Side Channel AttacksYoussef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar. 230-237 [doi]
• Interfacing and scheduling legacy code within the Canals frameworkAndreas Dahlin, Fareed Jokhio, Johan Lilius, Jérôme Gorin, Mickaël Raulet. 238-245 [doi]
• Range-free algorithm for energy-efficient indoor localization in Wireless Sensor NetworksVille Kaseva, Timo D. Hämäläinen, Marko Hännikäinen. 246-253 [doi]
• Application workload model generation methodologies for system-level design explorationJukka Saastamoinen, Jari Kreku. 254-260 [doi]
• A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methodsCarlo Condo, Guido Masera. 261-268 [doi]
• FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topologyMajdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser. 269-276 [doi]
• A new algorithm for realization of FIR filters using multiple constant multiplicationsMohsen Amiri Farahani, Eduardo Castillo Guerra, Bruce G. Colpitts. 277-283 [doi]
• Analyzing software inter-task communication channels on a clustered shared memory multi processor system-on-chipDaniela Genius, Nicolas Pouillon. 284-291 [doi]
• Multiplier free filter bank based concept for blocker detection in LTE systemsThomas Schlechter. 292-298 [doi]
• Practical monitoring and analysis tool for WSN testingMarkku Hänninen, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen. 299-306 [doi]
• High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGASana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. 308-315 [doi]
• Methodology for designing partially reconfigurable systems using transaction-level modelingFrançois Duhem, Fabrice Muller, Philippe Lorenzini. 316-322 [doi]
• A framework for the design of reconfigurable fault tolerant architecturesHung-Manh Pham, Sébastien Pillement, Olivier Pasquier, Sébastien LeNours. 324-331 [doi]
• High-level modelling and automatic generation of dynamicaly reconfigurable systemsGilberto Ochoa, El-Bay Bourennane, Hassan Rabah, Ouassila Labbani. 332-339 [doi]
• Systemc modelization for fast validation of imager architecturesYves Blanchard, Antoine Dupret, Arnaud Peizerat. 341-345 [doi]
• Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPUAntoine Pedron, Lionel Lacassagne, Franck Bimbard, Stéphane Le Berre. 347 [doi]