Table of Contents

• EDA challenges in the converging application worldRene Penning de Vries. 1 [doi]
• Sociology of design and EDAWalden C. Rhines. 2 [doi]
• Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chipMartino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano. 3-8 [doi]
• Efficient link capacity and QoS design for network-on-chipZvika Guz, Isask har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny. 9-14 [doi]
• Supporting task migration in multi-processor systems-on-chip: a feasibility studyStefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali. 15-20 [doi]
• Time domain model order reduction by wavelet collocation methodXuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang. 21-26 [doi]
• Large power grid analysis using domain decompositionQuming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen. 27-32 [doi]
• Analysis and modeling of power grid transmission linesJ. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne. 33-38 [doi]
• A logarithmic full-chip thermal analysis algorithm based on multi-layer Green s functionBaohua Wang, Pinaki Mazumder. 39-44 [doi]
• Large scale RLC circuit analysis using RLCG-MNA formulationYuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai. 45-46 [doi]
• Soft delay error analysis in logic circuitsBalkaran S. Gill, Christos A. Papachristou, Francis G. Wolff. 47-52 [doi]
• A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmapTsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang. 53-58 [doi]
• Analysis of the impact of bus implemented EDCs on on-chip SSNDaniele Rossi, Carlo Steiner, Cecilia Metra. 59-64 [doi]
• Optimal periodic testing of intermittent faults in embedded pipelined processor applicationsNektarios Kranitis, Andreas Merentitis, N. Laoutaris, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis. 65-70 [doi]
• Berger code-based concurrent error detection in asynchronous burst-mode machinesSobeeh Almukhaizim, Yiorgos Makris. 71-72 [doi]
• Two-phase resonant clocking for ultra-low-power hearing aid applicationsFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner. 73-78 [doi]
• A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemesSe-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo. 79-80 [doi]
• A single photon avalanche diode array fabricated in deep-submicron CMOS technologyCristiano Niclass, Maximilian Sergio, Edoardo Charbon. 81-86 [doi]
• MATLAB/Simulink for automotive systems designJon Friedman. 87-88 [doi]
• Model-based development of in-vehicle softwareMirko Conrad, Heiko Dörr. 89-90 [doi]
• Model-based testing of automotive electronicsKlaus Lamberg. 91 [doi]
• Designing signal processing systems for FPGAsJohn Heighton. 92 [doi]
• From UML/SysML to Matlab/Simulink: current state and future perspectivesYves Vanderperren, Wim Dehaene. 93 [doi]
• An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principlesEmmanuel Viaud, François Pêcheux, Alain Greiner. 94-99 [doi]
• Exploiting TLM and object introspection for system-level simulationGiovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington. 100-105 [doi]
• Efficient assertion based verification using TLMAli Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed. 106-111 [doi]
• Constructing portable compiled instruction-set simulators: an ADL-driven approachJoseph D Errico, Wei Qin. 112-117 [doi]
• A methodology for mapping multiple use-cases onto networks on chipsSrinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli. 118-123 [doi]
• Contrasting a NoC and a traditional interconnect fabric with layout awarenessFederico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo. 124-129 [doi]
• A low complexity heuristic for design of custom network-on-chip architecturesKrishnan Srinivasan, Karam S. Chatha. 130-135 [doi]
• A dynamically reconfigurable packet-switched network-on-chipThilo Pionteck, Carsten Albrecht, Roman Koch. 136-137 [doi]
• Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCsVahid Majidzadeh, Omid Shoaei. 138-143 [doi]
• Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensationMohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez. 144-149 [doi]
• Systematic stability-analysis method for analog circuitsGerd Vandersteen, Stephane Bronckers, Petr Dobrovolný, Yves Rolain. 150-155 [doi]
• ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuitsHui Zhang, Yang Zhao, Alex Doboli. 156-161 [doi]
• A synthesis tool for power-efficient base-band filter designV. Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D Amico, Andrea Baschirotto. 162-163 [doi]
• An efficient static algorithm for computing the soft error rates of combinational circuitsRajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester. 164-169 [doi]
• Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnectsMartin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra. 170-175 [doi]
• Evaluating coverage of error detection logic for soft errors using formal methodsUdo Krautz, Matthias Pflanz, Christian Jacobi 0002, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus. 176-181 [doi]
• Soft-error classification and impact analysis on real-time operating systemsN. Ignat, B. Nicolescu, Yvon Savaria, Gabriela Nicolescu. 182-187 [doi]
• 40Gbps de-layered silicon protocol engine for TCP recordH. Shrikumar. 188-193 [doi]
• A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applicationsAmilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller. 194-199 [doi]
• Disclosing the LDPC code decoder design spaceTorben Brack, Frank Kienle, Norbert Wehn. 200-205 [doi]
• Automating processor customisation: optimised memory access and resource sharingRobert G. Dimond, Oskar Mencer, Wayne Luk. 206-211 [doi]
• Automatic identification of application-specific functional units with architecturally visible storagePartha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi. 212-217 [doi]
• Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptographyJohann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma. 218-223 [doi]
• Simultaneously improving code size, performance, and energy in embedded processorsAhmad Zmily, Christos Kozyrakis. 224-229 [doi]
• Quantitative analysis of transaction level models for the AMBA busGunar Schirner, Rainer Dömer. 230-235 [doi]
• Combining simulation and formal methods for system-level performance analysisSimon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele. 236-241 [doi]
• Formal performance analysis and simulation of UML/SysML models for ESL designAlexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel. 242-247 [doi]
• Performance evaluation for system-on-chip architectures using trace-based transaction level simulationThomas Wild, Andreas Herkersdorf, Rainer Ohlendorf. 248-253 [doi]
• Is Network the next Big Idea in design?Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli. 254-256 [doi]
• Verifying analog oscillator circuits using forward/backward abstraction refinementGoran Frehse, Bruce H. Krogh, Rob A. Rutenbar. 257-262 [doi]
• Efficient AC analysis of oscillators using least-squares methodsTing Mei, Jaijeet S. Roychowdhury. 263-268 [doi]
• Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit intronsTrent McConaghy, Georges G. E. Gielen. 269-274 [doi]
• Top-down heterogeneous synthesis of analog and mixed-signal systemsEwout Martens, Georges G. E. Gielen. 275-280 [doi]
• Nonlinear model order reduction using remainder functionsJose A. Martinez, Steven P. Levitan, Donald M. Chiarulli. 281-282 [doi]
• Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesisHuiying Yang, Ranga Vemuri. 283-284 [doi]
• Hierarchy-aware and area-efficient test infrastructure design for core-based system chipsAnuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty. 285-290 [doi]
• Power constrained and defect-probability driven SoC test scheduling with test set partitioningZhiyuan He, Zebo Peng, Petru Eles. 291-296 [doi]
• Power-constrained test scheduling for multi-clock domain SoCsTomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara. 297-302 [doi]
• Reuse-based test access and integrated test scheduling for network-on-chipChunsheng Liu, Zach Link, Dhiraj K. Pradhan. 303-308 [doi]
• A design for failure analysis (DFFA) technique to ensure incorruptible signaturesSandip Kundu. 309-310 [doi]
• Test generation for combinational quantum cellular automata (QCA) circuitsPallav Gupta, Niraj K. Jha, Loganathan Lingappan. 311-316 [doi]
• Analysis and synthesis of quantum circuits by using quantum decision diagramsAfshin Abdollahi, Massoud Pedram. 317-322 [doi]
• Droplet routing in the synthesis of digital microfluidic biochipsFei Su, William L. Hwang, Krishnendu Chakrabarty. 323-328 [doi]
• Priority scheduling in digital microfluidics-based biochipsAndrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin. 329-334 [doi]
• A hybrid framework for design and analysis of fault-tolerant architecturesDebayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie Taylor, Paul Graham, Maya Gokhale. 335-336 [doi]
• Optical routing for 3D system-on-packageJacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim. 337-338 [doi]
• Distributed loop controller architecture for multi-threading in uni-threaded VLIW processorsPraveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest. 339-344 [doi]
• Compositional, efficient caches for a chip multi-processorAnca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven. 345-350 [doi]
• Efficient design space exploration of high performance embedded out-of-order processorsStijn Eyerman, Lieven Eeckhout, Koen De Bosschere. 351-356 [doi]
• Application-specific reconfigurable XOR-indexing to eliminate cache conflict missesHans Vandierendonck, Philippe Manet, Jean-Didier Legat. 357-362 [doi]
• A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architecturesMinwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi. 363-368 [doi]
• Compiler-driven FPGA-area allocation for reconfigurable computingElena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 369-374 [doi]
• Temporal partitioning for image processing based on time-space complexity in reconfigurable architecturesPaulo Sérgio B. do Nascimento, Manoel Eusebio de Lima. 375-380 [doi]
• System-level scheduling on instruction cell based reconfigurable systemsYing Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay. 381-386 [doi]
• DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit designMarkus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp. 387-392 [doi]
• Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systemsYing Wei, Hua Tang, Alex Doboli. 393-398 [doi]
• Double-sampling single-loop sigma-delta modulator topologies for broadband applicationsMohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez. 399-404 [doi]
• A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS processKambiz K. Moez, Mohamed I. Elmasry. 405-409 [doi]
• Bootstrapped full--swing CMOS driver for low supply voltage operationJosé C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi. 410-411 [doi]
• An effective technique for minimizing the cost of processor software-based diagnosis in SoCsPaolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda. 412-417 [doi]
• Timing-reasoning-based delay fault diagnosisKai Yang, Kwang-Ting Cheng. 418-423 [doi]
• Multiple-fault diagnosis based on single-fault activation and single-output observationYung-Chieh Lin, Kwang-Ting Cheng. 424-429 [doi]
• Software-based self-test of processors under power constraintsJun Zhou, Hans-Joachim Wunderlich. 430-435 [doi]
• Diagnosis of defects on scan enable and clock treesYu Huang, Keith Gallie. 436-437 [doi]
• Lock-free synchronization for dynamic embedded real-time systemsHyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen. 438-443 [doi]
• Performance analysis of greedy shapers in real-time systemsErnesto Wandeler, Alexander Maxiaguine, Lothar Thiele. 444-449 [doi]
• Improved offset-analysis using multiple timing-referencesRafik Henia, Rolf Ernst. 450-455 [doi]
• Procrastinating voltage scheduling with discrete frequency setsZhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron. 456-461 [doi]
• Communication and co-simulation infrastructure for heterogeneous system integrationGuang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli. 462-467 [doi]
• A SW performance estimation framework for early system-level-design using fine-grained instrumentationTorsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr. 468-473 [doi]
• A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case studyVíctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez. 474-479 [doi]
• Task-accurate performance modeling in SystemC for real-time multi-processor architecturesMartin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf. 480-481 [doi]
• Distributed object models for multi-processor SoC s, with application to low-power multimedia wireless systemsPierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo. 482-487 [doi]
• Virtual prototyping of embedded platforms for wireless and multimediaTim Kogel, Matthew Braun. 488-490 [doi]
• Application specific NoC designLuca Benini. 491-495 [doi]
• Automatic insertion of low power annotations in RTL for pipelined microprocessorsVinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.. 496-501 [doi]
• Power analysis of mobile 3D graphicsBren Mochocki, Kanishka Lahiri, Srihari Cadambi. 502-507 [doi]
• Automatic run-time selection of power policies for operating systemsNathaniel Pettis, Jason Ridenour, Yung-Hsiang Lu. 508-513 [doi]
• Energy reduction by workload adaptation in a multi-process environmentChangjiu Xian, Yung-Hsiang Lu. 514-519 [doi]
• Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-offJongsun Park, Jung Hwan Choi, Kaushik Roy. 520-521 [doi]
• Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmissionBrock J. LaMeres, Sunil P. Khatri. 522-527 [doi]
• Statistical timing analysis with path reconvergence and spatial correlationsLizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen. 528-532 [doi]
• Non-gaussian statistical interconnect timing analysisSoroush Abbaspour, Hanif Fatemi, Massoud Pedram. 533-538 [doi]
• Cell delay analysis based on rate-of-current changeShahin Nazarian, Massoud Pedram. 539-544 [doi]
• A practical method to estimate interconnect responses to variabilitiesFrank Liu. 545-546 [doi]
• Test and reliability challenges in automotive microelectronicsC. Sebeke, C. Jung, Klaus Harbich, S. Fuchs, J. Schwarz, Peter Göhner. 547 [doi]
• Exploring trade-off s between centralized versus decentralized automotive architectures using a virtual integration environmentSri Kanajan, Haibo Zeng, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli. 548-553 [doi]
• Management of complex automotive communication networksThomas Weber. 554-555 [doi]
• AutoVision: flexible processor architecture for video-assisted drivingAndreas Herkersdorf, Walter Stechele. 556 [doi]
• Domain specific model driven design for automotive electronic control unitsKlaus D. Müller-Glaser. 557 [doi]
• Electric and electronic vehicle architecture assessmentPascal Dégardins. 558 [doi]
• Automotive semi-conductor trend & challengesPatrick Leteinturier. 559 [doi]
• A systematic IP and bus subsystem modeling for platform-based system designJunhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim. 560-564 [doi]
• Heterogeneous behavioral hierarchy for system level designsHiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi. 565-570 [doi]
• Design with race-free hardware semanticsPatrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede. 571-576 [doi]
• Comfortable modeling of complex reactive systemsSteffen Prochnow, Reinhard von Hanxleden. 577-578 [doi]
• Faster exploration of high level design alternatives using UML for better partitionsWaseem Ahmed, Doug Myers. 579-580 [doi]
• A design flow for configurable embedded processors based on optimized instruction set extension synthesisRainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey. 581-586 [doi]
• Energy efficiency vs. programmability trade-off: architectures and design principlesPablo Robelly, Hendrik Seidel, K.-C. Chen, Gerhard Fettweis. 587-592 [doi]
• Advanced receiver algorithms for MIMO wireless communicationsAndreas Burg, Moritz Borgmann, Markus Wenk, Christoph Studer, Helmut Bölcskei. 593-598 [doi]
• Next generation architectures can dramatically reduce the 4G deployment cycleD. Shaver. 599 [doi]
• Automatic ADL-based operand isolation for embedded processorsAnupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 600-605 [doi]
• Power/performance hardware optimization for synchronization intensive applications in MPSoCsMatteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa. 606-611 [doi]
• An analytical state dependent leakage power model for FPGAsAkhilesh Kumar, Mohab Anis. 612-617 [doi]
• Smart bit-width allocation for low power optimization in a systemc based ASIC design environmentArindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou. 618-623 [doi]
• Value-based bit ordering for energy optimization of on-chip global signal busesKrishnan Sundaresan, Nihar R. Mahapatra. 624-625 [doi]
• Modeling multiple input switching of CMOS gates in DSM technology using HDMRJayashree Sridharan, Tom Chen. 626-631 [doi]
• A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuitsOliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner. 632-637 [doi]
• Using conjugate symmetries to enhance gate-level simulationsPeter M. Maurer. 638-643 [doi]
• HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slopeHessa Al-Junaid, Tom J. Kazmierski. 644-645 [doi]
• An improved RF loopback for test time reductionMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 646-651 [doi]
• Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clockingChunsheng Liu, Vikram Iyengar. 652-657 [doi]
• Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platformsGanesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee. 658-663 [doi]
• Pseudorandom functional BIST for linear and nonlinear MEMSAchraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur. 664-669 [doi]
• On-chip 8GHz non-periodic high-swing noise detectorMohamed Abbas, Makoto Ikeda, Kunihiro Asada. 670-671 [doi]
• Battery-aware code partitioning for a text to speech systemAnirban Lahiri, Anupam Basu, Monojit Choudhury, Srobona Mitra. 672-677 [doi]
• Performance optimization for energy-aware adaptive checkpointing in embedded real-time systemsZhongwen Li, Hong Chen, Shui Yu. 678-683 [doi]
• Software annotations for power optimization on mobile devicesRadu Cornea, Alexandru Nicolau, Nikil D. Dutt. 684-689 [doi]
• Dynamic partitioning of processing and memory resources in embedded MPSoC architecturesLiping Xue, Ozcan Ozturk, Feihui Li, Mahmut T. Kandemir, Ibrahim Kolcu. 690-695 [doi]
• Activity clustering for leakage management in SPMsMahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary Jane Irwin, Ibrahim Kolcu. 696-697 [doi]
• Adaptive data placement in an embedded multiprocessor thread libraryPhillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan. 698-699 [doi]
• COSMECA: application specific co-synthesis of memory and communication architectures for MPSoCSudeep Pasricha, Nikil D. Dutt. 700-705 [doi]
• Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systemsViacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng. 706-711 [doi]
• Communication architecture optimization: making the shortest path shorter in regular networks-on-chipÜmit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Naehyuck Chang. 712-717 [doi]
• Buffer space optimisation with communication synthesis and traffic shaping for NoCsSorin Manolache, Petru Eles, Zebo Peng. 718-723 [doi]
• Cooptimization of interface hardware and software for I/O controllersKuan Jen Lin, Shih Hao Huang, Shan Chien Fang. 724-725 [doi]
• Cross disciplinary aspects (4G wireless special day)Tobias G. Noll, Uwe Lambrette. 726 [doi]
• SoC: fuelling the hopes of the mobile industryUwe Lambrette, Booz Allen Hamilton. 727 [doi]
• Integrated data relocation and bus reconfiguration for adaptive system-on-chip platformsKrishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. 728-733 [doi]
• FPGA architecture characterization for system level performance analysisDouglas Densmore, Adam Donlin, Alberto L. Sangiovanni-Vincentelli. 734-739 [doi]
• Dynamic data type refinement methodology for systematic performance-energy design exploration of network applicationsAlexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. 740-745 [doi]
• Customization of application specific heterogeneous multi-pipeline processorsSwarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran. 746-751 [doi]
• Impact of bit-width specification on the memory hierarchy for a real-time video processing systemBenny Thörnberg, Mattias O Nils. 752-753 [doi]
• Efficient factorization of DSP transforms using taylor expansion diagramsJérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, D. Gomez-Prado, Serkan Askar. 754-755 [doi]
• Integrated placement and skew optimization for rotary clockingGanesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze. 756-761 [doi]
• Associative skew clock routing for difficult instancesMin-Seok Kim, Jiang Hu. 762-767 [doi]
• Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computationsShantanu Dutt, Hasan Arslan. 768-773 [doi]
• Defect tolerance of QCA tilesJing Huang, Mariam Momenzadeh, Fabrizio Lombardi. 774-779 [doi]
• Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuitsBipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy. 780-785 [doi]
• Novel designs for thermally robust coplanar crossing in QCASanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli. 786-791 [doi]
• Designing MRF based error correcting circuits for memory elementsKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky. 792-793 [doi]
• A time-triggered ethernet (TTE) switchKlaus Steinhammer, Petr Grillinger, Astrit Ademaj, Hermann Kopetz. 794-799 [doi]
• A time predictable Java processorMartin Schoeberl. 800-805 [doi]
• Optimizing the generation of object-oriented real-time embedded applications based on the real-time specification for JavaMarco A. Wehrmeister, Carlos Eduardo Pereira, Leandro Buss Becker. 806-811 [doi]
• Quantifier structure in search based procedures for QBFsEnrico Giunchiglia, Massimo Narizzano, Armando Tacchella. 812-817 [doi]
• Strong conflict analysis for propositional satisfiabilityHoonSang Jin, Fabio Somenzi. 818-823 [doi]
• Equivalence verification of arithmetic datapaths with multiple word-length operandsNamrata Shekhar, Priyank Kalla, Florian Enescu. 824-829 [doi]
• 4G applications, architectures, design methodology and tools for MPSoC830-831 [doi]
• Thermal resilient bounded-skew clock tree optimization methodologyAshutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino. 832-837 [doi]
• Exploring temperature-aware design in low-power MPSoCsGiacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini. 838-843 [doi]
• Adaptive chip-package thermal analysis for synthesis and designYonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick. 844-849 [doi]
• On-chip bus thermal analysis and optimizationFeng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. 850-855 [doi]
• Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologiesArijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy. 856-861 [doi]
• Low power synthesis of dynamic logic circuits using fine-grained clock gatingNilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia. 862-867 [doi]
• Enabling fine-grain leakage management by voltage anchor insertionPietro Babighian, Luca Benini, Alberto Macii, Enrico Macii. 868-873 [doi]
• Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systemsStylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias. 874-875 [doi]
• A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCsAndrea Alimonda, Andrea Acquaviva, Salvatore Carta, Alessandro Pisano. 876-877 [doi]
• 3D floorplanning with thermal viasEric Wong, Sung Kyu Lim. 878-883 [doi]
• Timing-driven cell layout de-compaction for yield optimization by critical area minimizationTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 884-889 [doi]
• Lens aberration aware timing-driven placementAndrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang. 890-895 [doi]
• On test conditions for the detection of open defectsBram Kruseman, Manuel Heiligers. 896-901 [doi]
• A compact model to identify delay faults due to crosstalkJosé Luis Rosselló, Jaume Segura. 902-906 [doi]
• Generation of broadside transition fault test sets that detect four-way bridging faultsIrith Pomeranz, Sudhakar M. Reddy. 907-912 [doi]
• Extraction of defect density and size distributions from wafer sort test resultsJeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton. 913-918 [doi]
• An interprocedural code optimization technique for network processors using hardware multi-threading supportHanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 919-924 [doi]
• An integrated scratch-pad allocator for affine and non-affine codeSumesh Udayakumaran, Rajeev Barua. 925-930 [doi]
• Dynamic scratch-pad memory management for irregular array access patternsGuilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mustafa Karaköy. 931-936 [doi]
• Restructuring field layouts for embedded memory systemsKeoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo Han. 937-942 [doi]
• Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilitiesPo-Kuan Huang, Soheil Ghiasi. 943-944 [doi]
• Dynamic code overlay of SDF-modeled programs on low-end embedded systemsHae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-min Sim, Soonhoi Ha. 945-946 [doi]
• optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAsBalasubramanian Sethuraman, Ranga Vemuri. 947-952 [doi]
• Hardware efficient architectures for Eigenvalue computationYang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley. 953-958 [doi]
• Memory centric thread synchronization on platform FPGAsChidamber Kulkarni, Gordon J. Brebner. 959-964 [doi]
• A parallel configuration model for reducing the run-time reconfiguration overheadYang Qu, Juha-Pekka Soininen, Jari Nurmi. 965-969 [doi]
• Wireless sensor networks and beyondPaul J. M. Havinga. 970 [doi]
• The ultra low-power wiseNET systemAmre El-Hoiydi, Claude Arm, R. Caseiro, Stefan Cserveny, Jean-Dominique Decotignie, Christian C. Enz, F. Giroud, S. Gyger, E. Leroux, Thierry Melly, Vincent Peiris, F. Pengg, P.-D. Pfister, N. Raemy, A. Ribordy, D. Ruffieux, P. Volet. 971-976 [doi]
• Fast-prototyping using the BTnode platformJan Beutel. 977-982 [doi]
• Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM designQikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy. 983-988 [doi]
• Architectural and technology influence on the optimal total power consumptionChristian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine. 989-994 [doi]
• Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignmentBehnam Amelifard, Farzan Fallah, Massoud Pedram. 995-1000 [doi]
• Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuitsKaushal R. Gandhi, Nihar R. Mahapatra. 1001-1006 [doi]
• On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTLNicola Bombieri, Franco Fummi, Graziano Pravadelli. 1007-1012 [doi]
• Functional verification methodology based on formal interface specification and transactor generationFelice Balarin, Roberto Passerone. 1013-1018 [doi]
• A coverage metric for the validation of interacting processesIan G. Harris. 1019-1024 [doi]
• New methods and coverage metrics for functional verificationVasco Jerinic, Jan Langer, Ulrich Heinkel, Dietmar Müller. 1025-1030 [doi]
• Classification trees for random tests and functional coverageAlexander Krupp, Wolfgang Müller 0003. 1031-1032 [doi]
• Efficient test-data compression for IP cores using multilevel Huffman codingXrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos. 1033-1038 [doi]
• Functional constraints vs. test compression in scan-based delay testingIlia Polian, Hideo Fujiwara. 1039-1044 [doi]
• Concurrent core test for SOC using shared test set and scan chain disableGang Zeng, Hideo Ito. 1045-1050 [doi]
• Efficient unknown blocking using LFSR reseedingSeongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar. 1051-1052 [doi]
• Coverage loss by using space compactors in presence of unknown valuesMango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng. 1053-1054 [doi]
• Online energy-aware I/O device scheduling for hard real-time systemsHui Cheng, Steve Goddard. 1055-1060 [doi]
• Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraintHeng-Ruey Hsu, Jian-Jia Chen, Tei-Wei Kuo. 1061-1066 [doi]
• Scheduling under resource constraints using dis-equationsHadda Cherroun, Alain Darte, Paul Feautrier. 1067-1072 [doi]
• Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platformsZhe Ma, Francky Catthoor. 1073-1078 [doi]
• Building a better Boolean matcher and symmetry detectorDonald Chai, Andreas Kuehlmann. 1079-1084 [doi]
• Optimizing sequential cycles through Shannon decomposition and retimingCristian Soviani, Olivier Tardieu, Stephen A. Edwards. 1085-1090 [doi]
• Efficient incremental clock latency scheduling for large circuitsChristoph Albrecht. 1091-1096 [doi]
• Analyzing timing uncertainty in mesh-based clock architecturesSubodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai. 1097-1102 [doi]
• Platform-based design of wireless sensor networks for industrial applicationsAlvise Bonivento, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 1103-1107 [doi]
• An environment for controlled experiments with in-house sensor networksVlado Handziski, Andreas Köpke, Andreas Willig, Adam Wolisz. 1108 [doi]
• Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day)Philippe Bonnet, Martin Leopold, K. Madsen. 1109 [doi]
• Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technologyLakshmi N. Chakrapani, Bilge E. S. Akgul, Suresh Cheemalavagu, Pinar Korkmaz, Krishna V. Palem, Balasubramanian Seshasayee. 1110-1115 [doi]
• Minimizing ohmic loss and supply voltage variation using a novel distributed power supply networkMark M. Budnik, Kaushik Roy. 1116-1121 [doi]
• An ultra low-power TLB designYen-Jen Chang. 1122-1127 [doi]
• Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithmsPeng Rong, Massoud Pedram. 1128-1133 [doi]
• A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point divisionDavid W. Matula, Lee D. McFearin. 1134-1138 [doi]
• On the relation between simulation-based and SAT-based diagnosisGörschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler. 1139-1144 [doi]
• An integrated open framework for heterogeneous MPSoC design space explorationFederico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini. 1145-1150 [doi]
• Parallel co-simulation using virtual synchronization with redundant host executionDohyung Kim, Soonhoi Ha, Rajesh Gupta. 1151-1156 [doi]
• An efficient and portable scheduler for RTOS simulation and its certified integration to SystemCHiroaki Nakamura, Naoto Sato, Naoshi Tabuchi. 1157-1158 [doi]
• Minimizing test power in SRAM through reduction of pre-charge activityLuigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard. 1159-1164 [doi]
• Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faultsVishal Suthar, Shantanu Dutt. 1165-1170 [doi]
• A concurrent testing method for NoC switchesMohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi. 1171-1176 [doi]
• A secure scan design methodologyDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. 1177-1178 [doi]
• RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabricsChen He, Margarida F. Jacome. 1179-1184 [doi]
• Layout driven data communication optimization for high level synthesisRyan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh. 1185-1190 [doi]
• Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuitsSaraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos. 1191-1196 [doi]
• Automatic generation of operation tables for fast exploration of bypasses in embedded processorsSanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek. 1197-1202 [doi]
• High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware countSoumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra. 1203-1204 [doi]
• Disjunctive image computation for embedded software verificationChao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta. 1205-1210 [doi]
• Distance-guided hybrid verification with GUIDOSmitha Shyam, Valeria Bertacco. 1211-1216 [doi]
• What lies between design intent coverage and model checking?Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti. 1217-1222 [doi]
• On the numerical verification of probabilistic rewriting systemsJounaïdi Ben Hassen, Sofiène Tahar. 1223-1224 [doi]
• Avoiding false negatives in formal verification for protocol-driven blocksGörschwin Fey, Daniel Große, Rolf Drechsler. 1225-1226 [doi]
• Low-power design tools: are EDA vendors taking this matter seriously?Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon. 1227 [doi]
• Formal verification of systemc designs using a petri-net based representationDaniel Karlsson, Petru Eles, Zebo Peng. 1228-1233 [doi]
• Monolithic verification of deep pipelines with collapsed flushingRoma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan. 1234-1239 [doi]
• Functional test generation using property decompositions for validation of pipelined processorsHeon-Mo Koo, Prabhat Mishra. 1240-1245 [doi]
• Proven correct monitors from PSL specificationsKatell Morin-Allory, Dominique Borrione. 1246-1251 [doi]
• Space of DRAM fault models and corresponding testingZaid Al-Ars, Said Hamdioui, A. J. van de Goor. 1252-1257 [doi]
• Automatic march tests generations for static linked faults in SRAMsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 1258-1263 [doi]
• Test compaction for transition faults under transparent-scanIrith Pomeranz, Sudhakar M. Reddy. 1264-1269 [doi]
• Test set enrichment using a probabilistic fault model and the theory of output deviationsZhanglei Wang, Krishnendu Chakrabarty, Michael Gössel. 1270-1275 [doi]
• Vulnerability analysis of L2 cache elements to single event upsetsHossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli. 1276-1281 [doi]
• Area-efficient error protection for cachesSoontae Kim. 1282-1287 [doi]
• Microarchitectural floorplanning under performance and thermal tradeoffMichael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh. 1288-1293 [doi]
• Optimizing high speed arithmetic circuits using three-term extractionAnup Hosangadi, Farzan Fallah, Ryan Kastner. 1294-1299 [doi]
• Efficient minimization of fully testable 2-SPP networksAnna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa. 1300-1305 [doi]
• Pre-synthesis optimization of multiplications to improve circuit performanceRafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida. 1306-1311 [doi]
• Crosstalk-aware domino logic synthesisYi-Yu Liu, TingTing Hwang. 1312-1317 [doi]
• TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoCWolfgang Klingauf, Hagen Gädke, Robert Günzel. 1318-1323 [doi]
• Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applicationsTero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen. 1324-1329 [doi]
• ASIP-based multiprocessor SoC design for simple and double binary turbo decodingOlivier Muller, Amer Baghdadi, Michel Jézéquel. 1330-1335 [doi]