Table of Contents

• A prototype VLSI chip architecture for JPEG image compressionMario Kovac, N. Ranganathan, Martin Zagar. 2-6 [doi]
• A variant of Cooley-Tuckey algorithm with local memory managementJ.-M. Bourguet, T. Nancy, Shao-Jun Wei, Jacques Leroy, Raymond Crappe. 7-11 [doi]
• Eliminating the Z-Buffer bottleneckGünter Knittel, Andreas Schilling. 12-17 [doi]
• Defect-oriented test methodology for complex mixed-signal circuitsF. C. M. Kuijstermans, Manoj Sachdev, A. P. Thijssen. 18-23 [doi]
• A design-for-test structure for optimising analogue and mixed signal IC testA. H. Bratt, Andrew M. D. Richardson, R. J. A. Harvey, A. P. Dorey. 24-33 [doi]
• Mixed-signal circuits and boards for high safety applicationsMarcelo Lubaszewski, Vladimir Kolarik, Salvador Mir, C. Nielsen, Bernard Courtois. 34-41 [doi]
• Exact scheduling strategies based on bipartite graph matchingAdwin H. Timmer, Jochen A. G. Jess. 42-47 [doi]
• On applicability of symbolic techniques to larger scheduling problemsIvan P. Radivojevic, Forrest Brewer. 48-53 [doi]
• Optimizing synchronous systems for multi-dimensional applicationsNelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao. 54-59 [doi]
• When clusters meet partitions: new density-based methods for circuit decompositionDennis J.-H. Huang, Andrew B. Kahng. 60-64 [doi]
• Circuit clustering for delay minimization under area and pin constraintsHonghua Yang, D. F. Wong. 65-70 [doi]
• Architecture driven k-way partitioning for multichip modulesBernhard M. Riess, A. A. Schoene. 71-79 [doi]
• Synthesis of multilevel fault-tolerant combinational circuitsAlessandro Bogliolo, Maurizio Damiani. 80-85 [doi]
• Improved technology mapping using a new approach to Boolean matchingB. Kapoor. 86-90 [doi]
• Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functionsRolf Drechsler, Bernd Becker. 91-99 [doi]
• Low-voltage low-power switched-current circuits and systemsNianxiong Tan, Sven Eriksson. 100-104 [doi]
• Low supply voltage, low noise fully differential programmable gain amplifiersAnton Pletersek, Drago Strle, Janez Trontelj. 105-112 [doi]
• A universal telephone audio circuit with loudhearing and handsfree operation in CMOS technologyK. Hayat-Dawoodi, O. Alminde, V. Kunc, M. Pauritsch. 113-118 [doi]
• A flexible topology selection program as part of an analog synthesis systemPetar Veselinovic, Domine Leenaerts, W. van Bokhoven, Francky Leyn, F. Proesmans, Georges G. E. Gielen, Willy Sansen. 119-125 [doi]
• Pseudo-exhaustive word-oriented DRAM testingMark G. Karpovsky, A. J. van de Goor, V. N. Yarmolik. 126-132 [doi]
• Functional test for shifting-type FIFOsA. J. van de Goor, Ivo Schanstra, Yervant Zorian. 133-138 [doi]
• A 370-MHz memory built-in self-test state machineR. Dean Adams, John Connor, Garret S. Koch, Luigi Ternullo Jr.. 139-143 [doi]
• Modeling and optimization of hierarchical synchronous circuitsBill Lin, Gjalt G. de Jong, Tilman Kolks. 144-149 [doi]
• Improving initialization through reversed retimingLeon Stok, Ilan Y. Spillinger, Guy Even. 150-154 [doi]
• Elimination of multi-cycle false paths by state encodingZafar Hasan, Maciej J. Ciesielski. 155-161 [doi]
• Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMCPierre Plaza, Juan Carlos Diaz, Fermín Calvo, L. A. Merayo, Maurizio Zamboni, P. Scarfone, M. Barbini. 162-166 [doi]
• Post-layout optimization of power and timing for ECL LSIsAkira Onozawa, Hitoshi Kitazawa, K. Kawai. 167-172 [doi]
• A 622/155 mbps ATM line terminator mono-chipMario Diaz-Nava, Didier Belot, P. Delerue, J. Bulone. 173-179 [doi]
• A unified model for co-simulation and co-synthesis of mixed hardware/software systemsCarlos A. Valderrama, Adel Changuel, P. V. Raghavan, Mohamed Abid, Tarek Ben Ismail, Ahmed Amine Jerraya. 180-184 [doi]
• SLIF: a specification-level intermediate format for system designFrank Vahid, Daniel D. Gajski. 185-189 [doi]
• Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systemsPeter Altenbernd. 190-197 [doi]
• High-level synthesis for easy testabilityMarie-Lise Flottes, D. Hammad, Bruno Rouzeyre. 198-206 [doi]
• Sequential logic minimization based on functional testabilityFranco Fummi, Donatella Sciuto, Micaela Serra. 207-211 [doi]
• A Gauss-elimination based PRPG for combinational circuitsLi-Ren Huang, Sy-Yen Kuo, Ing-Yi Chen. 212-217 [doi]
• Mixed-signal modelling in VHDL for system-on-chip applicationsF. Pichon, S. Blanc, B. Candaele. 218-222 [doi]
• Run-time consistency checking in discrete simulation modelsJ. W. G. Fleurkens, C. A. J. van Eijk, Jochen A. G. Jess. 223-227 [doi]
• Delay models for the sea-of-wires array synthesis systemIng-Yi Chen, Geng-Lin Chen, Sy-Yen Kuo. 228-233 [doi]
• A unified scheduling model for high-level synthesis and code generationAugusli Kifli, G. Goosens, Hugo De Man. 234-238 [doi]
• A BDD-based frontend for retargetable compilersRainer Leupers, Peter Marwedel. 239-243 [doi]
• Efficient code generation for in-house DSP-coresMarino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note. 244-251 [doi]
• Complexity of sequential ATPGThomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski. 252-261 [doi]
• Improved sequential ATPG using functional observation information and new justification methodsJaehong Park, Chanhee Oh, M. Ray Mercer. 262-266 [doi]
• GARDA: a diagnostic ATPG for large synchronous sequential circuitsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 267-273 [doi]
• Controlling change propagation and project policies in IC designYves Mathys, Marc Morgan, Salma Soudagar. 274-279 [doi]
• Generic design flows for project management in a framework environmentEwa Kwee-Christoph, Fridtjof Feldbusch, Ramayya Kumar, Arno Kunzmann. 280-284 [doi]
• Enhanced functionality by coupling the JESSI-COMMON-Framework with an ECAD frameworkArno Kunzmann, Ralf Seepold. 285-293 [doi]
• Enhanced testing performance via unbiased test setsLi-C. Wang, M. Ray Mercer, Thomas W. Williams. 294-302 [doi]
• A testability measure for hierarchical design environmentsM. H. C. Lee, D. L. Tao. 303-307 [doi]
• Gate delay fault test generation for non-scan circuitsG. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus. 308-313 [doi]
• Verifying real-time properties of MOS-transistor circuitsJürgen Frößl, Thomas Kropf. 314-319 [doi]
• Using symbolic techniques to find the maximum clique in very large sparse graphsFulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 320-324 [doi]
• Checking signal transition graph implementability by symbolic BDD traversalAlex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Enric Pastor, Oriol Roig, Alexandre Yakovlev. 325-332 [doi]
• Proving testing preorders for process algebra descriptionsFulvio Corno, M. Cusinato, M. Ferrero, Paolo Prinetto. 333-339 [doi]
• Architectural exploration for datapaths with memory hierarchyNancy D. Holmes, Daniel D. Gajski. 340-344 [doi]
• Design reuse through high-level library mappingPradip K. Jha, Nikil D. Dutt. 345-350 [doi]
• Automatic clock tree generation in ASIC designsAlessandro Balboni, Claudio Costi, A. Pellencin, M. Quadrini, Donatella Sciuto. 351-357 [doi]
• Area versus detection latency trade-offs in self-checking memory designO. Kebichi, Yervant Zorian, Michael Nicolaidis. 358-362 [doi]
• Self-checking architectures for fast Hartley transformJamel M. Tahir, Satnam Singh Dlay, Raouf N. Gorgui-Naguib, Oliver R. Hinton. 363-371 [doi]
• Built-in intermediate voltage testing for CMOS circuitsJing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu. 372-377 [doi]
• Design and test of the PowerPC 603 microprocessorE. Kofi Vida-Torku, Charles H. Malley, Sung Park, R. Reed. 378-384 [doi]
• An ASIC design for real-time image processing in industrial applicationsMaurizio Valle, Giovanni Nateri, Daniele D. Caviglia, Giacomo M. Bisio, Luciano Briozzo. 385-390 [doi]
• Rapid prototype of a hardware emulator for a SIMD processor arrayDavid L. Andrews, Andrew Wheeler, Barry Wealand, Cliff Kancler. 391-397 [doi]
• Analysis and reduction of glitches in synchronous networksJeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess. 398-403 [doi]
• Decomposition of logic functions for minimum transition activityRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 404-410 [doi]
• Prediction of interconnect delay in logic synthesisHorng-Fei Jyu, Sharad Malik. 411-417 [doi]
• A BIST approach to delay fault testing with reduced test lengthBernd Wurth, Karl Fuchs. 418-423 [doi]
• BIST hardware generator for mixed test schemeChristian Dufaza, H. Viallon, Cyril Chevalier. 424-430 [doi]
• Accumulator-based BIST approach for stuck-open and delay fault testingIoannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis. 431-437 [doi]
• How many decomposition types do we need? [decision diagrams]Bernd Becker, Rolf Drechsler. 438-443 [doi]
• VERIFUL: VERIfication using FUnctional LearningRajarshi Mukherjee, Jawahar Jain, Masahiro Fujita. 444-448 [doi]
• Implicit manipulation of polynomials using zero-suppressed BDDsS. Minato. 449-457 [doi]
• Automatic test vector generation for mixed-signal circuitsBechir Ayari, Naim Ben Hamida, Bozena Kaminska. 458-463 [doi]
• Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuitsChristian Sebeke, J. P. Teixeira, Michael J. Ohletz. 464-468 [doi]
• Achieving simulation-based test program verification and fault simulation capabilities for mixed-signal systemsPascal Caunegre, Claude Abraham. 469-479 [doi]
• The effect of pin constraints on layout areaBernd Schürmann, Joachim Altmeyer. 480-485 [doi]
• EMC-driven midway routing on PCBsH. Schmidt, Dirk Theune, Ralf Thiele, Thomas Lengauer. 486-491 [doi]
• A hybrid hierarchical approach for multi-layer global routingMasayuki Hayashi, Shuji Tsukiyama. 492-497 [doi]
• Software estimation using a generic-processor modelJie Gong, Daniel D. Gajski, Sanjiv Narayan. 498-502 [doi]
• Describing instruction set processors using nMLA. Fauth, J. Van Praet, M. Freericks. 503-507 [doi]
• Incorporating compiler feedback into the design of ASIPsFrederick Onion, Alexandru Nicolau, Nikil Dutt. 508-515 [doi]
• An efficient method for computing exact path delay fault coverageB. Kapoor. 516-520 [doi]
• Bit parallel test pattern generation for path delay faultsManfred Henftling, Hannes Wittman. 521-525 [doi]
• A trace-based method for delay fault diagnosis in synchronous sequential circuitsPatrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez. 526-533 [doi]
• Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structuresLuis Miguel Silveira, Mattan Kamon, Jacob White. 534-538 [doi]
• On software development to support statistical simulation of analogue circuitsE. Driouk, O. Jarov, A. Sukhodolsky. 539-543 [doi]
• Multilevel thermal simulation of MCM's by system 'MONSTR-M'Vladimir A. Koval, Dmytro V. Fedasyuk. 544-549 [doi]
• Combining MBP-speculative computation and loop pipelining in high-level synthesisUlrich Holtmann, Rolf Ernst. 550-556 [doi]
• PPS: a pipeline path-based schedulerMaher Rahmouni, Ahmed Amine Jerraya. 557-561 [doi]
• Balancing structural hazards and hardware cost of pipelined processorsAlbert E. Casavant. 562-567 [doi]
• Correlation between I/sub DDQ/ testing quality and sensor accuracyMarcello Dalpasso, Michele Favalli, Piero Olivo. 568-572 [doi]
• Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensorsHans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Calderón. 573-580 [doi]
• A built-in quiescent current monitor for CMOS VLSI circuitsAntonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura. 581-587 [doi]
• High speed communications links for ASICsIan Montandon, David Burrows, Kenneth J. Hunt. 588 [doi]
• TRJM: a high speed programmable ATM-SDH mapperJesus Crespo, F. Calvo, Juan I. Solana, Rafael Caravantes, J. L. Conesa. 589 [doi]
• Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesisGeorge-Peter K. Economou, John Ant. Hallas, Evaggelinos P. Mariatos, Constantinos E. Goutis. 590 [doi]
• Integration of an expert system for analogue layout synthesis into a commercial CAD frameworkD. A. Bensouiah, R. J. Mack, R. E. Massara. 591 [doi]
• Synthesis for testability: circuits derived from ordered Kronecker functional decision diagramsBernd Becker, Rolf Drechsler. 592 [doi]
• Efficient synthesis of fault-tolerant controllersR. Rochet, Régis Leveugle, Gabriele Saucier. 593 [doi]
• A balanced multilevel decomposition methodHenry Selvaraj, Tadeusz Luba. 594 [doi]
• A precise event-driven circuit simulator based on predicted fan-in voltagesHisanori Fujisawa, Fumiyo Kawafuji, Tomoyasu Kitaura, Tetsuro Kage. 595 [doi]
• Network initialization in a switch-level simulatorArjan J. van Genderen. 596-597 [doi]
• SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defectsWitold A. Pleskacz, Wieslaw Kuzmicz. 598 [doi]
• A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICsMichele Favalli, Bruno Riccò, L. Penza. 599 [doi]
• A method for testability analysis and BIST insertion at the RTLJoan Carletta, Christos A. Papachristou. 600 [doi]
• Thermal test and monitoring [microelectronic structures]Vladimir Székely, Márta Rencz. 601 [doi]
• On testability of checkable digital circuits under pseudorandom signalsA. Romankevich, V. Groll. 602 [doi]
• Imperfect linear duplication of combinational circuitsR. Kh. Latypov, Ye. L. Stolov. 603 [doi]
• Test preparation methodology for high coverage of physical defects in CMOS digital ICsMarcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira. 604 [doi]
• Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosisJ. Soares Augusto, C. F. Beltrá Almeida. 605 [doi]
• A comparative study of algorithms for A/D converter performance evaluation by statistical analysisDominique Dallet, G. Franco, Philippe Marchegay, C. Morandi. 606 [doi]
• A histogram method for analog-digital converters testing in time and spectral domainV. Zagursky, N. Semyonova, M. Sirovatkina. 607 [doi]