Table of Contents

• The Guiding Light for Chip TestingSandip Kundu. 1 [doi]
• The Wall Ahead is Made of RubberKrisztián Flautner. 2 [doi]
• The Quest for Test: Will Redundancy Cover All?Hans A. R. Manhaeve. 3 [doi]
• Deep-Submicron MOS Transistor Matching: A Case StudyDimitar P. Dimitrov. 4-7 [doi]
• Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS TechnologyHåvard Pedersen Alstad, Snorre Aunet. 8-11 [doi]
• Improving Circuit Security against Power Analysis Attacks with Subthreshold OperationHåvard Pedersen Alstad, Snorre Aunet. 12-13 [doi]
• Controllable Local Clock Signal Generator for Deep Submicron GALS ArchitecturesArtur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz. 14-17 [doi]
• Computation of a nonlinear squashing function in digital neural networksVladimir Havel, Karel K. Vlcek. 18-21 [doi]
• An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAsStanislaw Deniziak, Mariusz Wisniewski. 22-25 [doi]
• Portable Measurement Equipment for Continuous Biomedical Monitoring using MicroelectrodesLibor Majer, Viera Stopjaková. 26-29 [doi]
• Design of Erasure Codes for Digital Multimedia TransmittingKonstantin V. Shinkarenko, Karel K. Vlcek. 30-33 [doi]
• Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based CircuitsJorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 34-37 [doi]
• A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature VariationsTomasz Borejko, Witold A. Pleskacz. 38-43 [doi]
• Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage ScalingMin Bao, Alexandru Andrei, Petru Eles, Zebo Peng. 44-49 [doi]
• Gain reduction by gate-leakage currents in regulated cascodesFranz Schlögl, Kerstin Schneider-Hornstein, Horst Zimmermann. 50-53 [doi]
• A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing AnglesThomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke. 54-58 [doi]
• Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output ImpedanceWeixun Yan, Horst Zimmermann. 59-63 [doi]
• A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA IIIKuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-lung Lo, Wei-Bin Yang, Jiunn-Way Miaw. 64-67 [doi]
• Incremental SAT Instance Generation for SAT-based ATPGDaniel Tille, Rolf Drechsler. 68-73 [doi]
• Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAsAndrzej Krasniewski. 74-79 [doi]
• Analysis of the influence of intermittent faults in a microcontrollerJoaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil. 80-85 [doi]
• Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR PlatformMartin Palkovic, Hans Cappelle, Miguel Glassee, Bruno Bougard, Liesbet Van der Perre. 86-91 [doi]
• Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on ChipZhonghai Lu, Lei Xia, Axel Jantsch. 92-97 [doi]
• MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoCRishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi. 98-103 [doi]
• Rapid Prototyping of NoC Architectures from a SystemC SpecificationStanislaw Deniziak, Robert Tomaszewski. 104-109 [doi]
• Novel Hardware Implementation of Adaptive Median FiltersZdenek Vasícek, Lukás Sekanina. 110-115 [doi]
• A New Design Technique for Weakly Indicating Function BlocksPadnamabhan Balasubramanian, D. A. Edwards. 116-121 [doi]
• Fast Boolean Minimizer for Completely Specified FunctionsPetr Fiser, Pemysl Rucký, Irena Vanová. 122-127 [doi]
• The HDL and FE Thermal Modeling of Heterogeneous SystemsGrzegorz Janczyk, Tomasz Bieniek. 128-131 [doi]
• A System-On-Chip for Wireless Body Area Sensor Network NodeZoran Stamenkovic, Goran Panic, Günter Schoof. 132-135 [doi]
• Mixed-Signal DFT for fully testable ASICFrantisek Reznicek. 136-139 [doi]
• On Minimizing RTOS Aperiodic Tasks Server Energy ConsumptionKarel Dudacek. 140-143 [doi]
• Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor SystemsMiroslav Manik, Elena Gramatová. 144-145 [doi]
• A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point UnitsVirgil E. Petcu, Alexandru Amaricai, Mircea Vladutiu. 146-149 [doi]
• Design of Time-to-Digital Converter Output InterfaceMarek Miskowicz. 150-153 [doi]
• Design and Simulation of Runtime Reconfigurable SystemsThilo Pionteck, Carsten Albrecht, Roman Koch, Torben Brix, Erik Maehle. 154-157 [doi]
• Modeling and observing the jitter in ring oscillators implemented in FPGAsBoyan Valtchanov, Alain Aubert, Florent Bernard, Viktor Fischer. 158-163 [doi]
• Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number GeneratorMilos Drutarovsky, Michal Varchola. 164-169 [doi]
• Various MDCT implementations in 0.35µm CMOSPeter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz. 170-173 [doi]
• Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS TechnologyKurt Schweiger, Horst Zimmermann. 174-177 [doi]
• Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAsLeos Kafka. 178-181 [doi]
• Implementation of Dynamically Reconfigurable Test Architecture for FPGA CircuitsMartin Rozkovec. 182-185 [doi]
• A Partial Scan Based Test Generation for Asynchronous CircuitsDilip P. Vasudevan, Aristides Efthymiou. 186-189 [doi]
• Efficient Allocation of Verification Resources using Revision History InformationJosé Augusto Miranda Nacif, Thiago Silva, Andréa Iabrudi Tavares, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.. 190-194 [doi]
• Ad-Hoc Translations to Close Verilog Semantics GapChristian Haufe, Frank Rogin. 195-200 [doi]
• Code Coverage Analysis using High-Level Decision DiagramsJaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee. 201-206 [doi]
• Probabilistic Model Checking and Reliability of ResultsRalf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker. 207-212 [doi]
• Network Probe for Flexible Flow MonitoringMartin Zádník, Jan Korenek, Petr Kobierský, Ondej Lengál. 213-218 [doi]
• NetCOPE: Platform for Rapid Development of Network ApplicationsTomás Martínek, Martin Kosek. 219-224 [doi]
• IP-based Systematic Design of Power-and Matching-limited CircuitsDavid Smola, Ludk Pantucek. 225-230 [doi]
• A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID ApplicationsMarco Bucci, Raimondo Luzzi, Santos Torres Vargas. 231-234 [doi]
• Calculating the fault coverage for dual neighboring faults using single stuck-at fault patternsJan Schat. 235-240 [doi]
• Evaluation of the Iddq Signature in devices with Gauss-distributed background currentJan Schat. 241-246 [doi]
• Interconnect Faults Identification and Localization Using Modified Ring LFSRsAndrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec. 247-250 [doi]
• Testing an Emergency Luminaire Circuit Using a Fault Dictionary ApproachDimitrios K. Konstantinou, Michael Dimopoulos, Dimitris K. Papakostas, Alkis A. Hatzopoulos, Alexios Spyronasios. 251-254 [doi]
• Reduction of Test Vectors Volume by Means of Gate-Level ReconfigurationLukás Starecek, Lukás Sekanina, Zdenek Kotásek. 255-268 [doi]
• Built-In Current Monitor for IDDQ Testing in CMOS 90 nm TechnologyMarcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková. 259-262 [doi]
• Diagnosis of Realistic Defects Based on the X-Fault ModelIlia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen. 263-266 [doi]
• Improving Fault Tolerance by Using Reconfigurable Asynchronous CircuitsWerner Friesenbichler, Thomas Panhofer, Martin Delvai. 267-270 [doi]
• Web-Based Framework for Parallel Distributed TestEero Ivask, Jaan Raik, Raimund Ubar. 271-274 [doi]
• Calculation of LFSR Seed and Polynomial Pair for BIST ApplicationsArtur Jutman, Anton Tsertov, Raimund Ubar. 275-278 [doi]
• Excitation optimization in fault diagnosis of analog electronic circuitsLukas Chruszczyk, Jerzy Rutkowski. 279-282 [doi]
• Virtual Testing Environment for A/D Converters in Verilog-A and Maple PlatformOndrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka. 283-286 [doi]
• Efficient Estimation of Die-Level Process Parameter Variations via the EM-AlgorithmAmir Zjajo, Shaji Krishnan, José Pineda de Gyvez. 287-292 [doi]
• Experimental Analog Circuit for Parametric Test Methods Efficiency EvaluationJuraj Brenkus, Viera Stopjaková, Jozef Mihálov. 293-298 [doi]
• The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response FeaturesPiotr Jantos, Damian Grzechca, Tomasz Golonek, Jerzy Rutkowski. 299-303 [doi]
• A novel method for test and calibration of capacitive accelerometers with a fully electrical setupNorbert Dumas, Florence Azaïs, Frédérick Mailly, Andrew Richardson, Pascal Nouet. 304-309 [doi]
• On-chip Integration of Magnetic Force Sensing Current MonitorsMartin Donoval, Martin Daricek, Viera Stopjaková, Juraj Marek. 310-313 [doi]
• A Cost Effective BIST Second-Order Sigma-Delta-ModulatorHao-Chiao Hong, Sheng-Chuan Liang, Hong-Chin Song. 314-319 [doi]
• SoC Symbolic Simulation: a case study on delay fault testingAlberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi. 320-325 [doi]
• SoCECT: System on Chip Embedded Core TestMichael Higgins, Ciaran MacNamee, Brendan Mullane. 326-331 [doi]
• Optimal Backgrounds Selection for Multi Run Memory TestingIreneusz Mrozek, Vyacheslav Yarmolik. 332-338 [doi]
• Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCsWilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda. 339-344 [doi]