Table of Contents

• Design technology and the cloudRaul Camposano. 1 [doi]
• Cost effective scaling to 22nm and below technology nodesAndrzej J. Strojwas. 2 [doi]
• Future of EDA: Usual suspect or silent hero for successful semiconductor business?Jürgen Alt. 3 [doi]
• SiGe BiCMOS platform - baseline technology for More Than Moore process module integrationBernd Tillack. 4 [doi]
• Testing and design-for-testability solutions for 3D integrated circuitsKrishnendu Chakrabarty. 5 [doi]
• Introduction to the SystemC AMS extension standardKarsten Einwich. 6-8 [doi]
• Small scale energy harvesting - principles, practices and future trendsDong S. Ha. 9 [doi]
• Conversion and interfacing techniques for asynchronous circuitsMarkus Ferringer. 11-16 [doi]
• A system-level platform for dependability enhancement and its analysis for mixed-signal SoCsMuhammad Aamir Khan, Hans G. Kerkhoff. 17-22 [doi]
• Dual use of power lines for data communications in microprocessorsVipul Chawla, Dong Sam Ha. 23-28 [doi]
• PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applicationsKrzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz. 29-34 [doi]
• Design-for-Test method for high-speed ADCs: Behavioral description and optimizationYolanda Lechuga, Román Mozuelos, Mar Martínez, Salvador Bracho. 35-40 [doi]
• High performance adaptive sensor interface design through model based estimation of analog non-idealitiesSumit Adhikari, Muhammad Farooq, Jan Haase, Christoph Grimm. 41-46 [doi]
• Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encodersXuan-Tu Tran, Van-Huan Tran. 47-52 [doi]
• Towards an unified IP verification and robustness analysis platformDavid Hély, Vincent Beroulle, Feng Lu, José Ramón García Oya. 53-58 [doi]
• An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platformWlodzimierz Wrona, Pawel Duc, Lukasz Barcik, Wojciech Pietrasina. 59-63 [doi]
• An analog perspective on device reliability in 32nm high-κ metal gate technologyFlorian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel. 65-70 [doi]
• Increasing the efficiency of analog OBIST using on-chip compensation of technology variationsDaniel Arbet, Juraj Brenkus, Gábor Gyepes, Viera Stopjaková. 71-74 [doi]
• A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variationsMichal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz. 75-79 [doi]
• Defect-oriented module-level fault diagnosis in digital circuitsSergei Kostin, Raimund Ubar, Jaan Raik. 81-86 [doi]
• Efficient diagnostics algorithms for regular computing structuresMiroslav Manik, Elena Gramatová. 87-92 [doi]
• SAT-based analysis of sensitisable pathsMatthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker. 93-98 [doi]
• Wireless wafer-level testing of integrated circuits via capacitively-coupled channelsDae-Young Lee, David D. Wentzloff, John P. Hayes. 99-104 [doi]
• Optimal number and placement of Through Silicon Vias in 3D Network-on-ChipThomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen. 105-110 [doi]
• Decoupling capacitance boosting for on-chip resonant supply noise reductionJinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada. 111-114 [doi]
• An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillatorTetsuya Iizuka, Kunihiro Asada. 115-120 [doi]
• Low-complexity integrated circuit aging monitorAleksandar Simevski, Rolf Kraemer, Milos Krstic. 121-125 [doi]
• A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technologyJakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski. 131-134 [doi]
• Fault tolerance of SRAM-based FPGA via configuration framesFarid Lahrach, Abderrahim Doumar, Eric Châtelet. 139-142 [doi]
• A new hierarchical built-in self-test with on-chip diagnosis for VLIW processorsMarkus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus. 143-146 [doi]
• A chaos-based pseudo-random bit generator implemented in FPGA devicePawel Dabal, Ryszard Pelka. 151-154 [doi]
• Software defined radio - design and implementation of complete platformPawel Pawlowski, Adam Dabrowski, Piotr Skrzypek, Piotr Roszak, Andrzej Palejko, Tomasz Walenciak, Mateusz Mor. 155-158 [doi]
• Influence of parasitic memory effect on single-cell faults in SRAMsSandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell. 159-162 [doi]
• Behavioral model of TRNG based on oscillator rings implemented in FPGAKnut Wold, Slobodan Petrovic. 163-166 [doi]
• Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemCOliver Stecklina, Frank Vater, Thomas Basmer, Erik Bergmann, Hannes Menzel. 167-170 [doi]
• Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operationsTsuyoshi Iwagaki, Kewal K. Saluja. 175-178 [doi]
• Decomposition of multi-output logic function in Reed-Muller spectral domainStefan Kolodzinski, Edward Hrynkiewicz. 179-182 [doi]
• Functional enhancements of TMR for power efficient and error resilient ASIC designsHagen Sämrow, Claas Cornelius, Philipp Gorski, Jakob Salzmann, Andreas Tockhorn, Dirk Timmermann. 183-188 [doi]
• A study of path delay variations in the presence of uncorrelated power and ground supply noiseAida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. 189-194 [doi]
• Muller C-elements based on minority-3 functions for ultra low voltage suppliesHans Kristian Otnes Berge, Amir Hasanbegovic, Snorre Aunet. 195-200 [doi]
• Power consumption traces realignment to improve differential power analysisGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal. 201-206 [doi]
• Fault injection analysis of transient faults in clustered VLIW processorsLuca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda. 207-212 [doi]
• Implementation of Selective Fault Tolerance with conventional synthesis toolsMichael Augustin, Michael Gössel, Rolf Kraemer. 213-218 [doi]
• Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repairTobias Koal, Heinrich Theodor Vierhaus. 219-224 [doi]
• An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errorsAbdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf. 225-230 [doi]
• Hardware architecture for packet classification with prefix coloringViktor Pus, Michal Kajan, Jan Korenek. 231-236 [doi]
• Communication modelling and synthesis for NoC-based systems with real-time constraintsMihkel Tagel, Peeter Ellervee, Thorsten Hollstein, Gert Jervan. 237-242 [doi]
• Optimization of message encryption for distributed embedded systems with real-time constraintsKe Jiang, Petru Eles, Zebo Peng. 243-248 [doi]
• Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenarioCarmen Garcia, Antonio Rubio. 249-254 [doi]
• Characterization of digital cells for statistical testFabian Hopsch, Michael Lindig, Bernd Straube, Wolfgang Vermeiren. 255-260 [doi]
• A variation-aware adaptive voltage scaling technique based on in-situ delay monitoringMartin Wirnshofer, Leonhard Heiß, Georg Georgakos, Doris Schmitt-Landsiedel. 261-266 [doi]
• Receiver OEIC using a bipolar translinear loopArtur Marchlewski, Horst Zimmermann, Ingrid Jonak-Auer, Ewald Wachmann. 267-270 [doi]
• DODT: Increasing requirements formalism using domain ontologies for improved embedded systems developmentStefan Farfeleder, Thomas Moser, Andreas Krall, Tor Stålhane, Herbert Zojer, Christian Panis. 271-274 [doi]
• Abstract modeling and simulation based selective estimationYaseen Zaidi, Sumit Adhikari, Christoph Grimm. 275-278 [doi]
• Fast just-in-time translated simulator for ASIP designZdenek Prikryl, Jakub Kroustek, Tomas Hruska, Dusan Kolár. 279-282 [doi]
• CAD tool for PLL DesignKrzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz. 283-286 [doi]
• Verification of JPEG2000 encoder based on rate and distortion curve analysisDamian Modrzyk, Michal Staworko. 289-292 [doi]
• Failure probability of SRAM-FPGA systems with Stochastic Activity NetworksCinzia Bernardeschi, Luca Cassano, Andrea Domenici. 293-296 [doi]
• Improving performance of robust Self Adaptive Caches by optimizing the switching algorithmLiviu Agnola, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan. 297-300 [doi]
• Sample synchronization of multiple multiplexed DA and AD converters in FPGAsThilo Ohlemueller, Markus Petri. 301-304 [doi]
• Hardware efficient design of Variable Length FFT ProcessorVinay Gautam, Kailash Chandra Ray, Pauline Haddow. 309-312 [doi]
• High-performance hardware accelerators for sorting and managing prioritiesValery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson. 313-318 [doi]
• Precise IPv4/IPv6 packet generator based on NetCOPE platformJirí Matousek, Pavol Korcek. 319-324 [doi]
• Effective hash-based IPv6 longest prefix matchJiri Tobola, Jan Korenek. 325-328 [doi]
• Stacking order impact on overall 3D die-to-wafer Stacked-IC costMottaqiallah Taouil, Said Hamdioui. 335-340 [doi]
• A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuitsYiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos. 341-346 [doi]
• Optimized embedded memory diagnosisMauricio de Carvalho, Paolo Bernardi, Matteo Sonza Reorda, Nicola Campanelli, Tamas Kerekes, Davide Appello, Mario Barone, Vincenzo Tancorre, Marco Terzi. 347-352 [doi]
• Optimized march test flow for detecting memory faults in SRAM devices under bit line couplingLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. 353-358 [doi]
• On using a SPICE-like TSTAC™ eFlash model for design and testPierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez. 359-364 [doi]
• Statistical analysis of 6T SRAM data retention voltage under process variationElena Ioana Vatajel, Joan Figueras. 365-370 [doi]
• Decreasing test time by scan chain reorganizationPavel Bartos, Zdenek Kotásek, Jan Dohnal. 371-374 [doi]
• Max-Fill: A method to generate high quality delay testsXiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz. 375-380 [doi]
• Measurement point selection for in-operation wear-out monitoringUrban Ingelsson, Shih-Yen Chang, Erik Larsson. 381-386 [doi]
• Test vector overlapping based compression tool for narrow test access mechanismJiri Jenícek, Martin Rozkovec, Ondrej Novák. 387-392 [doi]
• A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis applicationFarhad Goodarzy, Efstratios Skafidas. 393-394 [doi]
• Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologiesGábor Gyepes, Juraj Brenkus, Daniel Arbet, Viera Stopjaková. 395-396 [doi]
• Advanced fault tolerant bus for multicore system implemented in FPGAMartin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek. 397-398 [doi]
• Validation and optimization of TMR protections for circuits in radiation environmentsOscar Ruano, Juan Antonio Maestro, Pedro Reviriego. 399-400 [doi]
• Reduction of FPGA resources for regular expression matching by relation similarityVlastimil Kosar, Jan Korenek. 401-402 [doi]
• Low-power quadrature VCO design for medical implant communication serviceJeong-Ki Kim, Jihoon Jeong, Dong Sam Ha, Hyung-Soo Lee. 403-404 [doi]
• Current sensing methodology for completion detection in self-timed systemsLukás Nagy, Viera Stopjaková. 405-406 [doi]
• A wireless ECG sensor node based on Huffman data encoderUros Pesovic, Sinisa Randic, Zoran Stamenkovic. 411-412 [doi]
• Advanced rectifier and driver for analog VU meterMartin Pospisilik, Milan Adamek. 413-414 [doi]
• Automatic property generation for the formal verification of bus bridgesMathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler. 417-422 [doi]
• Probabilistic equivalence checking based on high-level decision diagramsAnton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik. 423-428 [doi]
• Proof certificates and non-linear arithmetic constraintsStefan Kupferschmid, Bernd Becker, Tino Teige, Martin Fränzle. 429-434 [doi]
• TLM protocol compliance checking at the Electronic System LevelMohamed Bawadekji, Daniel Große, Rolf Drechsler. 435-440 [doi]
• Error recovery technique for coarse-grained reconfigurable architecturesMuhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement. 441-446 [doi]
• Behavior of CMOS polymorphic circuits in high temperature environmentRichard Ruzicka, Vaclav Simek, Lukás Sekanina. 447-452 [doi]
• Dynamic placement applications into Self Adaptive network on FPGAPetr Honzík, Jirí Kadlec. 453-456 [doi]
• Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platformsAndré Seffrin, Sorin A. Huss. 457-462 [doi]