Table of Contents

• On the Reliable Performance of Sequential Adders for Soft ComputingJinghang Liang, Jie Han, Fabrizio Lombardi. 3-10 [doi]
• Decimal Hamming: A Software-Implemented Technique to Cope with Soft ErrorsCostas Argyrides, Ronaldo Rodrigues Ferreira, Carlos Arthur Lang Lisbôa, Luigi Carro. 11-17 [doi]
• Impact of Aging Phenomena on Soft Error SusceptibilityDaniele Rossi, Martin Omaña, Cecilia Metra, Alessandro Paccagnella. 18-24 [doi]
• An Area Effective Parity-Based Fault Detection Technique for FPGAsGabriel L. Nazar, Luigi Carro. 27-33 [doi]
• A Reliability-Aware Partitioner for Multi-FPGA PlatformsCristiana Bolchini, Chiara Sandionigi. 34-40 [doi]
• Fine-Grained Software-Based Self-Repair of VLIW ProcessorsMario Schölzel. 41-49 [doi]
• A New Algorithm for Post-Silicon Clock Measurement and TuningZahra Lak, Nicola Nicolici. 53-59 [doi]
• A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS CircuitsHao Chen, Jie Han, Fabrizio Lombardi. 60-67 [doi]
• NBTI Monitoring and Design for Reliability in Nanoscale CircuitsSeyab Khan, Nor Zaidi Haron, Said Hamdioui, Francky Catthoor. 68-76 [doi]
• Biased Voting for Improved Yield in Nanoscale FabricsMd. Muwyid U. Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna, Csaba Andras Moritz. 79-85 [doi]
• CNT-count Failure Characteristics of Carbon Nanotube FETs under Process VariationsBehnam Ghavami, Mohsen Raji, Hossein Pedram, Omid Naghshineh Arjmand. 86-92 [doi]
• Optimal Test Set Selection for Fault Diagnosis ImprovementLuca Amati, Cristiana Bolchini, Fabio Salice. 93-99 [doi]
• Impact of Synthesis Constraints on Error Propagation Probability of Digital CircuitsDaniel B. Limbrick, Suge Yue, William H. Robinson, Bharat L. Bhuva. 103-111 [doi]
• Reducing Test Power for Embedded MemoriesAhmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui. 112-119 [doi]
• Hierarchical Embedded Logic Analyzer for Accurate Root-Cause AnalysisMohammad Hossein Neishaburi, Zeljko Zilic. 120-128 [doi]
• A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic GateChandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis. 131-138 [doi]
• A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal DevicesNivesh Rai, Hamidreza Hashempour, Yizi Xing, Bram Kruseman, Said Hamdioui. 139-145 [doi]
• Templated-Based Asynchronous Design for Testable and Fail-Safe OperationMasoud Zamani, Hossein Pedram, Fabrizio Lombardi. 146-152 [doi]
• A Practical Approach to Single Event Transients Analysis for Highly Complex DesignsDan Alexandrescu, Enrico Costenaro, Michael Nicolaidis. 155-163 [doi]
• Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set OperationsUljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee. 164-170 [doi]
• An Application-Level Dependability Analysis Framework for Embedded SystemsCristiana Bolchini, Antonio Miele. 171-178 [doi]
• Creating Defect Tolerance in Microfluidic Capacitive/Photonic BiosensorsGlenn H. Chapman, Bonnie L. Gray, Vijay K. Jain. 181-189 [doi]
• Efficient Function Mapping in Nanoscale Crossbar ArchitectureJoon-Sung Yang, Rudrajit Datta. 190-196 [doi]
• Modeling Yield of Self-Healing Carbon Nanotubes/Silicon-Nanowire FET-based NanoarrayJ. Seol, Noh-Jin Park, K. M. George, Nohpill Park. 197-205 [doi]
• Control-Flow Recovery Validation Using Microarchitectural InvariantsJavier Carretero, Jaume Abella, Xavier Vera, Pedro Chaparro. 209-216 [doi]
• Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence TreeXun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy. 217-225 [doi]
• On the Modeling of Gate Delay Faults by Means of Transition Delay FaultsPaolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch. 226-232 [doi]
• Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power GridVijay K. Jain, Glenn H. Chapman. 235-242 [doi]
• A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect ToleranceE. MacLean, V. K. Jain. 243-251 [doi]
• Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot ConditionDaniele Giaffreda, Martin Omaña, Daniele Rossi, Cecilia Metra. 252-258 [doi]
• A Probabilistic Approach to Diagnose SETsSreenivas Gangadhar, Spyros Tragoudas. 261-267 [doi]
• A Soft Error Tolerance Estimation Method for Sequential CircuitsMasayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga. 268-276 [doi]
• A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-ChipAmlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh. 277-285 [doi]
• Deletion/Insertion/Reversal Error Correcting Codes for Bit-Patterned Media RecordingMasato Inoue, Haruhiko Kaneko. 286-293 [doi]
• Error Resilient Infrastructure for Data Transfer in a Distributed Neutron DetectorLuigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. 294-301 [doi]
• A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron TechnologiesRodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 302-308 [doi]
• On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOSNachiket Rajderkar, Marco Ottavi, Salvatore Pontarelli, Jie Han, Fabrizio Lombardi. 309-315 [doi]
• On the Feasibility of Built-In Self Repair for Logic CircuitsTobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus. 316-324 [doi]
• Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA PlatformMehran Mozaffari Kermani, Arash Reyhani-Masoleh. 325-331 [doi]
• X-Stacking - A Method for Reducing Control Data for Output CompactionRudrajit Datta, Nur A. Touba. 332-338 [doi]
• An Architecture to Enable Life Cycle Testing in CMPsRance Rodrigues, Israel Koren, Sandip Kundu. 341-348 [doi]
• Analyzing the Sensitivity to Faults of Synchronization PrimitivesPaolo Roberto Grassi, Mariagiovanna Sami, Ettore Speziale, Michele Tartara. 349-355 [doi]
• Characterizing System-Level Vulnerability for Instruction Caches against Soft ErrorsShuai Wang. 356-363 [doi]
• Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic ApproachRudrajit Datta, Nur A. Touba. 367-373 [doi]
• SoC Mixed-Signal Dependability Enhancement: A Strategy from Design to End-of-LifeMuhammad Aamir Khan, Hans G. Kerkhoff. 374-381 [doi]
• Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable ArchitecturesSven Eisenhardt, Anja Küster, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel. 382-388 [doi]
• An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication SystemsJorge Luis Lagos-Benites, Michelangelo Grosso, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini, V. A. Avantaggiati. 391-398 [doi]
• Debug Aware AXI-based Network InterfaceMohammad Hossein Neishaburi, Zeljko Zilic. 399-407 [doi]
• Predicting Pixel Defect Rates Based on Image Sensor ParametersGlenn H. Chapman, Jenny Leung, Ana Namburete, Israel Koren, Zahava Koren. 408-416 [doi]
• On the Delay Analysis of Defective CNTFETs with Undeposited CNTsGeunho Cho, Fabrizio Lombardi. 419-425 [doi]
• Online Fault Detection in Reversible LogicNoor M. Nayeem, Jacqueline E. Rice. 426-434 [doi]
• Online Missing/Repeated Gate Faults Detection in Reversible CircuitsMasoud Zamani, Mehdi Baradaran Tahoori. 435-442 [doi]
• A Fault Tolerant Hierarchical Network on Chip Router ArchitectureMohammad Hossein Neishaburi, Zeljko Zilic. 445-453 [doi]
• A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-ChipKhalid Latif 0002, Amir-Mohammad Rahmani, Ethiopia Nigussie, Hannu Tenhunen, Tiberiu Seceleanu. 454-462 [doi]
• Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private MemoriesMasashi Imai, Tomohiro Yoneda. 463-471 [doi]
• Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-ChipsHiroshi Kutami, Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi, Takeshi Hattori. 472-480 [doi]