Table of Contents

• Title Page [doi]
• Conference Committees [doi]
• Message from the Program Chair [doi]
• Copyright [doi]
• Multi-media Applications and Imprecise ComputationMelvin A. Breuer. 2-7 [doi]
• Wireless Sensor Systems - Constraints and OpportunitiesDirk Timmermann. 8 [doi]
• BIST Technique for GALS SystemsMilos Krstic, Eckhard Grass. 10-16 [doi]
• Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic ProgrammingTun Li, Yang Guo, Gongjie Liu, Sikun Li. 17-25 [doi]
• P2I: An Innovative MDA Methodology for Embedded Real-Time SystemArnaud Cuccuru, Robert de Simone, Thierry Saunier, Günther Siegel, Yves Sorel. 26-33 [doi]
• Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy ReductionDong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles. 34-41 [doi]
• A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit RepresentationAndreas Lindahl, Lars Bengtsson. 42-47 [doi]
• Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number SystemMark G. Arnold. 48-55 [doi]
• Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BISTPeter Filter, Hana Kubatova. 56-63 [doi]
• Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault DetectionLucía Costas, Juan J. Rodríguez-Andina. 64-71 [doi]
• Improved Fault Emulation for Synchronous Sequential CircuitsJaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar. 72-78 [doi]
• Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC DesignsJoachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz. 79-82 [doi]
• Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test EnvironmentZhiyuan He, Gert Jervan, Zebo Peng, Petru Eles. 83-87 [doi]
• Hardware Virtual Components Compliant with Communication System StandardsNabil Abdelli, Pierre Bomel, Emmanuel Casseau, Anne-Marie Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno. 88-95 [doi]
• High-Level Synthesis in Latency Insensitive System MethodologyPierre Bomel, Nabil Abdelli, Eric Martin, Anne-Marie Fouilliart, Emmanuel Boutillon, Philippe Kajfasz. 96-101 [doi]
• Embedded Object ArchitectureTero Vallius, Juha Röning. 102-107 [doi]
• An Effective Framework for Enabling the Reuse of External Soft IPSoujanna Sarkar, Subash G. Chandar. 108-113 [doi]
• A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDsDariusz Kania, Józef Kulisz, Adam Milik. 114-121 [doi]
• An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOSMd. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu. 122-126 [doi]
• State Assignment for PAL-based CPLDsRobert Czerwinski, Dariusz Kania. 127-134 [doi]
• Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane ArrayVladimir Ciric, Ivan Milentijevic. 135-138 [doi]
• Automatic Design of Binary and Multiple-Valued Logic Gates on RTD SeriesKrzysztof S. Berezowski, Sarma B. K. Vrudhula. 139-143 [doi]
• Design of Transport Triggered Architecture Processors for Wireless EncryptionPanu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen. 144-152 [doi]
• RF CMOS Circuits for Ad-Hoc Networks and Wearable ComputingC. Siu, Soraya Kasnavi, Kris Iniewski, F. Nabki. 153-160 [doi]
• Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDLPetri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen. 161-164 [doi]
• Optimization of Electronic Power Consumption in Wireless Sensor NodesS. Jayapal, S. Ramachandran, R. Bhutada, Yiannos Manoli. 165-169 [doi]
• Vital Signs Remote Management System for PDAsDanielly Cruz, Edna Barros. 170-175 [doi]
• MA2TG: A Functional Test Program Generator for Microprocessor VerificationTun Li, Dan Zhu, Yang Guo, Gongjie Liu, Sikun Li. 176-183 [doi]
• A processor for testing mixed-signal cores in System-on-ChipFrancisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos. 184-191 [doi]
• Functional Test Generation Remote ToolEduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas. 192-195 [doi]
• Validation of Embedded Systems Using Formal Method Aided SimulationDaniel Karlsson, Petru Eles, Zebo Peng. 196-201 [doi]
• VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC CodesMassimo Rovini, Nicola E. L Insalata, Francesco Rossi, Luca Fanucci. 202-209 [doi]
• A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG CompressorLuciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva. 210-213 [doi]
• Reconfigurable Parallel Approximate String Matching on FPGAsJin Hwan Park. 214-217 [doi]
• Efficient MLP Digital Implementation on FPGASalvatore Vitabile, Vincenzo Conti, Fulvio Gennaro, Filippo Sorbello. 218-222 [doi]
• Designing a Binary Neural Network Co-processorMichael Freeman, Jim Austin. 223-227 [doi]
• Efficient Host-Independent Coprocessor Architecture for Speech Coding AlgorithmsHamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari. 227-230 [doi]
• Massively Parallel Hardware Architecture for Genetic AlgorithmsNadia Nedjah, Luiza de Macedo Mourelle. 231-234 [doi]
• Implementation of a block based neural branch predictorOswaldo Cadenas, Graham M. Megson, Daniel Jones. 235-238 [doi]
• PRUS - Processor Network for Digital Circuit ImplementationStanley Hyduke, Vladimir Hahanov, Volodymyr Obrizan, Olesya Guz. 239-242 [doi]
• Capturing Processor Architectures from Protocol Processing Applications: a Case StudySeppo Virtanen, Jani Paakkulainen, Tero Nurmi. 243-246 [doi]
• Yield-aware FloorplanningZhaojun Wo, Israel Koren, Maciej J. Ciesielski. 247-253 [doi]
• Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor NodesKashif Virk, Jan Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet. 254-260 [doi]
• An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval PatternY. Ghiassi, Mohammad M. M. Rad, Mohammad S. Nikjoo, Ali Hesam Mohseni, Babak Hossein Khalaj. 261-266 [doi]
• Wireless Sensor Network Implementation for Industrial Linear Position MeteringMikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen. 267-275 [doi]
• MemBIST Applet for Learning Principles of Memory Testing and Generating Memory BISTMária Fischerová, Martin Simlastík. 276-281 [doi]
• High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced TrafficMiguel Pereira, Enrique Soto, Juan J. Rodríguez-Andina, F. Javier González-Castaño. 282-288 [doi]
• Delay Testability Properties of Circuits Implementing Threshold and Symmetric FunctionsPiotr Patronik. 289-297 [doi]
• A New Architecture for fast Arithmetic Coding in H.264 Advanced Video CoderRoberto R. Osorio, Javier D. Bruguera. 298-305 [doi]
• Exploring Graphics Processor Performance for General Purpose ApplicationsPedro Trancoso, Maria Charalambous. 306-313 [doi]
• Hardware-Based Implementation of the Common Approximate Substring AlgorithmKenneth B. Kent, Sharon Van Schaick, Jacqueline E. Rice, Patricia A. Evans. 314-321 [doi]
• Cost-effective VLSI Design of Non Linear Image Processing FiltersSergio Saponara, Michele Cassiano, Stefano Marsi, Riccardo Coen, Luca Fanucci. 322-329 [doi]
• Java to Hardware Compilation for non Data Flow ApplicationsPer Andersson, Krzysztof Kuchcinski. 330-337 [doi]
• Formal Communication Semantics of SystemC:::FL:::Ka L. Man. 338-345 [doi]
• A high-level tool for the design of custom image processing systemsSérgio Martins, José Carlos Alves. 346-349 [doi]
• Throughput of Streaming Applications Running on a Multiprocessor ArchitectureNikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen. 350-355 [doi]
• A Constraints Programming Approach for Fabric Cell SynthesisChristophe Wolinski, Krzysztof Kuchcinski. 356-363 [doi]
• SystemC-based Design Methodology for Reconfigurable System-on-ChipYang Qu, Kari Tiensyrjä, Juha-Pekka Soininen. 364-371 [doi]
• Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing SystemsFarhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi. 372-378 [doi]
• An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable SystemsGhaffari Fakhreddine, Michel Auguin, Mohamed Abid, Benjemaa Maher. 379-382 [doi]
• Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAsMiguel L. Silva, João Canas Ferreira. 383-387 [doi]
• Predictable embedding of large data structures in multiprocessor networks-on-chipSander Stuijk, Twan Basten, Bart Mesman, Marc Geilen. 388-396 [doi]
• An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable ArchitecturesFredy Rivera, Milagros Fernández, Nader Bagherzadeh. 396-402 [doi]
• Optimization of a Bus-based Test Data Transportation Mechanism in System-on-ChipAnders Larsson, Erik Larsson, Petru Eles, Zebo Peng. 403-411 [doi]
• An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime PlatformArtur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov. 412-419 [doi]
• Educational Tool for the Demonstration of DfT Principles Based on Scan MethodologiesJosef Strnadel, Zdenek Kotásek. 420-427 [doi]
• Remote Path Delay Fault SimulationOystein Gjermundnes, Einar J. Aas. 428-434 [doi]
• Internet-Based IC Technology Design and SimulationV. Nelayev, V. Stempitsky, K. Kudin. 435-441 [doi]
• Decomposition of Multi-Output Functions for CPLDsDariusz Kania, Adam Milik, Józef Kulisz. 442-449 [doi]
• High-quality Sub-function Construction in the Information-driven Circuit Synthesis with GatesLech Józwiak, Szymon Bieganski. 450-459 [doi]
• Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA ArchitecturesMariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba. 460-466 [doi]
• On LUT Cascade Realizations of FIR FiltersTsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki. 467-475 [doi]
• Dynamic Split: Flexible Border Between Instruction and Data CachePedro Trancoso. 476-483 [doi]
• ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time ApplicationsArnaldo Oliveira, Valery Sklyarov, António de Brito Ferrari. 484-491 [doi]
• Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors ArraysDanilo Pani, Giuseppe Passino, Luigi Raffo. 492-499 [doi]