Abstract is missing.
- Layout-aware laser fault injection simulation and modeling: From physical level to gate levelFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Guillaume Hubert. 1-6 [doi]
- Bio-electronic interaction: principle and applicationsN. Lewis. 1 [doi]
- Slack removal for enhanced reliability and trustAbishek Ramdas, Samah Mohamed Saeed, Ozgur Sinanoglu. 1-4 [doi]
- Low voltage analog readout channel based on gain-boosted amplifiersJuan Antonio Gómez Galán, R. Lopez-Ahumada, Trinidad Sanchez-Rodriguez, M. Sanchez-Raya, Manuel Pedro, Raúl Jiménez. 1-6 [doi]
- Stuck-at fault diagnosis in scan chainsHelen-Maria Dounavi, Yiorgos Tsiatouhas. 1-6 [doi]
- MicroElectrode Array (MEA), a way to access to the Neural code for in-vitro and in-vivo applications, principle and fabricationLionel Rousseau, Gaelle Lissorgues. 1 [doi]
- Evaluation of image deblurring algorithms for real-time applicationsGiuseppe Airo Farulla, Marco Indaco, Daniele Rolfo, Ludovico Orlando Russo, Pascal Trotta. 1-6 [doi]
- 2nd generation bilayer graphene transistors for applications in nanoelectronicsP. J. Wessely, Udo Schwalke. 1-3 [doi]
- Generation and validation of multioperand carry save adders from the webMinas Dasygenis. 1-6 [doi]
- Linking aging measurements of health-monitors and specifications for multi-processor SoCsHans G. Kerkhoff, Jinbo Wan, Yong Zhao. 1-6 [doi]
- Power consumption analysis for mesh based FPGASonda Chtourou, Mohamed Abid, Zied Marrakchi, Habib Mehrez. 1-5 [doi]
- Easily verified IP watermarkingAnastasios Bikos, Haridimos T. Vergos. 1-2 [doi]
- Laser attacks on integrated circuits: From CMOS to FD-SOIJean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noemie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale. 1-6 [doi]
- 3D/ 2.5D stacked IC cost modeling and test flow selectionSaid Hamdioui. 1 [doi]
- DTIS 2014 forewordIoannis Voyiatzis, Michel Renovell, Mohamed Masmoudi, Paolo Prinetto, Giorgio Di Natale. 1 [doi]
- Physical design and testing of Nano Magnetic architecturesGiovanna Turvani, A. Tohti, M. Bollo, Fabrizio Riente, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni. 1-6 [doi]
- A survey on simulation-based fault injection tools for complex systemsMaha Kooli, Giorgio Di Natale. 1-6 [doi]
- Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimizationBernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer. 1-10 [doi]
- Dependence of annealing temperature on cluster formation during in situ growth of CNTsMartin Keyn, Andreas Kramer, Udo Schwalke. 1-5 [doi]
- Accumulator-based self-adjusting output data compression for embedded word-organized DRAMsIoannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou. 1-6 [doi]
- n+1 multiply-add-add unitsConstantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis. 1-4 [doi]
- An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systemsLuca Cassano, Dario Cozzi, Dirk Jungewelter, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi. 1-6 [doi]
- Recent advances in single- and multi-site test optimization for DVS-based SoCsXrysovalantis Kavousianos, Krishnendu Chakrabarty. 1-6 [doi]
- Towards resilient cyber-physical systems: The ADREAM projectJean Arlat, Michel Diaz, Mohamed Kaâniche. 1-5 [doi]
- Memristor based memories: Technology, design and testSaid Hamdioui, Hassan Aziza, Georgios Ch. Sirakoulis. 1-7 [doi]
- Low overhead output response compaction in RAS architecturesIoannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou. 1-3 [doi]
- An electrostatically doped planar device conceptTillmann Krauss, Frank Wessely, Udo Schwalke. 1-4 [doi]
- Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGAVinod Pangracious, Zied Marrakchi, Nizar Beltaief, Habib Mehrez, Umer Farooq. 1-6 [doi]
- Investigating large integer arithmetic on Intel Xeon Phi SIMD extensionsAnastasis Keliris, Michail Maniatakos. 1-6 [doi]
- ATPG for transition faults of pipelined threshold logic circuitsAshok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis. 1-5 [doi]
- Electromagnetic attacks on embedded devices: A model of probe-circuit power couplingDiego Alberto, Paolo Maistri, Régis Leveugle. 1-6 [doi]
- On error models for RTL security evaluationsPierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hély, Vincent Beroulle. 1-6 [doi]
- Doubly-segmented current-steering DAC calibrationGildas Leger. 1-6 [doi]
- Bio-impedance spectroscopyEric McAdams. 1-2 [doi]
- A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space explorationMinas Dasygenis. 1-2 [doi]
- Accurate multiplexed test structure for threshold voltage matching evaluationLoic Welter, Philippe Dreux, Jordan Innocenti, Hassen Aziza, Jean Michel Portal. 1-6 [doi]
- New floating inductance simulator employing a single ZC-VDTA and one grounded capacitorArda Guney, Hakan Kuntman. 1-2 [doi]