Table of Contents

• The Reinvention of the MicroprocessorChris Rowen. 3-6
• Using configurable processors for high-efficiency multiple-processor systemsChris Rowen. 7-10
• Promises and Pitfalls of Reconfigurable SupercomputingMaya Gokhale, Christopher Rickett, Justin L. Tripp, Chung Hsu, Ronald Scrofano. 11-20
• The Case for High Level Programming Models for Reconfigurable ComputersDavid L. Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp. 21-32
• Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable ComputingBrian Holland, James Greco, Ian A. Troxel, Gabe Barfield, Vikas Aggarwal, Alan D. George. 33-41
• Searching RC5-Keys with Distributed Reconfigurable ComputingDirk Koch, Matthiaas Koerber, Jürgen Teich. 42-48
• Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task AssignmentVincent Nollet, Prabhat Avasare, Diederik Verkest, Henk Corporaal. 49-55
• A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration OverheadRajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik. 56-62
• SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable ArchitectureCarlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto. 63-69
• Relocation and Defragmentation for Heterogeneous Reconfigurable SystemsMarkus Koester, Heiko Kalte, Mario Porrmann. 70-76
• Cache Architectures for Reconfigurable HardwareSebastian Lange, Martin Middendorf. 77-83
• RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart CameraYvan Eustache, Jean-Philippe Diguet, Milad El Khodary. 84-92
• Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection AlgorithmCraig Ulmer, Adrian Javelo. 93-102
• An FPGA based Co-Design Architecture for MIMO Lattice DecodersCao Liang, Jing Ma, Xin-Ming Huang. 103-109
• Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium ArchitectureGerard K. Rauwerda, Gerard J. M. Smit, Casper R. W. van Benthem, Paul M. Heysters. 110-116
• A Column Arrangement Algorithm for a Coarse-grained Reconfigurable ArchitectureYuanqing Guo, Cornelis Hoede, Gerard J. M. Smit. 117-122
• Delgado-Frias, Jonathan Larson, Mitchell Myjak: Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable ArchitectureJosé. 123-129
• A Parametric Study of Scalable Interconnects on FPGAsDaihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano. 130-135
• Group-Alignment based Accurate Floating-Point Summation on FPGAsChuan He, Guan Qin, Mi Lu, Wei Zhao. 136-142
• Code Partitioning for Reconfigurable High-Performance Computing: A Case StudyVolodymyr V. Kindratenko. 143-152
• Efficient FPGA-based Implementations of the MIMO-OFDM Physical LayerJeoong Sung Park, Hong-Jip Jung, Viktor K. Prasanna. 153-163
• Process Isolation for Reconfigurable HardwareHerwin Chan, Patrick Schaumont, Ingrid Verbauwhede. 164-170
• Hydra: An Energy-efficient and Reconfigurable Network InterfaceMarcel D. van de Burgwal, Gerard J. M. Smit, Gerard K. Rauwerda, Paul M. Heysters. 171-177
• Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdogan. 178-183
• Reconfigurable Acceleration of Robust Frequency-Domain Echo CancellationChun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk. 184-190
• Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable LogicJoshua Noseworthy, Miriam Leeser. 191-197
• Differential Reconfiguration Architecture suitable for a Holographic MemoryMinoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi. 198-206
• Multi-Mode Operator for SHA-2 Hash FunctionsRyan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon. 207-210
• Intrinsic Embedded Hardware Evolution of Block-based Neural NetworksSaumil Merchant, Gregory D. Peterson, Seong Kong. 211-214
• Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number GenerationYu Bi, Gregory D. Peterson, G. Lee Warren, Robert J. Harrison. 215-218
• Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar SystemsMohammad Samie, Gabriel Dragffy, Ebrahim Farjah. 219-222
• Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable ComputersXuejun Liang, Qutaibah M. Malluhi. 223-226
• GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow GraphsFarhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki Murakami, Hamid Noori. 227-230
• Architectural Support for Runtime 2D Partial ReconfigurationFei Wang, Jack S. N. Jean. 231-236
• Logic Synthesis and Place-and-Route Environment for ORGAsMinoru Watanabe, Fuminori Kobayashi. 237-238
• Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate ArrayMinoru Watanabe, Fuminori Kobayashi. 239-240
• A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning SystemVinay Sriram, David Kearney. 241-243
• An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number GeneratorVinay Sriram, David Kearney. 244-246
• A Generic Lookup Cache Architecture for Network Processing ApplicationsJanardhan Singaraju, John A. Chandy. 247-248
• Synthesis of Object Oriented Models on Reconfigurable HardwareGiovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto. 249-250
• A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAsAlireza Sarvi, Jenny Fan, Reto Stamm. 251-252
• Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case StudyHeng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler. 253-256
• The Era of Reconfigurable ComputingPaul M. Heysters. 257-264
• Dynamic Scheduling and Resource Management in Heterogeneous Computing Environments with Reconfigurable HardwareSteven Smith. 265-271
• Coarse-Grained Reconfigurable Computing for Power Aware ApplicationsPaul M. Heysters. 272