Abstract is missing.
- Algorithm Design for Reconfigurable Computing SystemsViktor K. Prasanna. 3
- It s Like Deja-Vu All over Again ... AgainJose L. Muñoz. 4
- Future Directions in Reconfigurable ComputingRahul Razdan. 5
- FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication SystemsChristophe Jégo. 9-18
- Japanese Dynamically Reconfigurable ProcessorsHideharu Amano. 19-28
- How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor ExtensionsChristophe Wolinski, Krzysztof Kuchcinski, Kevin Martin, Erwan Raffin, François Charot. 29-42
- Bio-inspired Systems: Self-adaptability from Chips to Sensor-network ArchitecturesGilles Sassatelli. 45-54
- Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano EraJürgen Becker. 55-66
- A Design Environment for Bio-Inspired Cellular ArchitecturesPierre-André Mudry, Gianluca Tempesti. 67-80
- Networked Self-adaptive Systems: An Opportunity for Configuring in the LargeJean-Philippe Diguet, Linfeng Ye, Yvan Eustache, Jeremie Crenne, Pierre Bomel, Guy Gogniat, Jorgiano Vidal, Florent de Lamotte. 81-90
- Adaptive Processing Architectures for the Ultimate Scaling of the CMOS WorldLuigi Carro, Monica Magalhães Pereira. 91-97
- Element CXI: Exploring Element Computing in AcademiaPeter Athanas. 101
- The Effect of Parameterization on a Reconfigurable Implementation of PIVAbderrahmane Bennis, Miriam Leeser, Gilead Tadmor. 105-111
- Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable ProcessorsToru Sano, Yoshiki Saito, Hideharu Amano. 112-118
- Using Run-time Reconfiguration for Energy Savings in Parallel Data ProcessingMadhura Purnaprajna, Christopher Pohl, Mario Porrmann, Ulrich Rückert. 119-125
- Application Experiments: MPPA and FPGAPhilip Top, Maya Gokhale. 126-135
- Bit Error Rate, Power and Area Analysis of Multiple FPGA Implementations of Underwater FSKYing Li, Bridget Benson, Ryan Kastner, Xing Zhang. 136-142
- An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol ConvertersShota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama. 145-150
- A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular SetYosuke Kawanaka, Shin ichi Wakabayashi, Shinobu Nagayama. 151-157
- A Novel Multicontext Coarse-Grained Join Accelerator for Column-Oriented DatabasesPranav Vaidya, Jaehwan John Lee. 158-164
- Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable ArchitecturesKenneth Rovers, Marcel D. van de Burgwal, Jan Kuper, Gerard J. M. Smit. 167-173
- SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable SystemsPaolo Roberto Grassi, Marco D. Santambrogio, Jens Hagemeyer, Christopher Pohl, Mario Porrmann. 174-180
- Supporting Operating Systems for Reconfigurable Computing: A Distributed Service Oriented ApproachFernando Rincón, Julio Dondo, Jesús Barba, Francisco Moya, Juan Carlos López. 181-187
- Harnessing Human Computation Cycles for the FPGA Placement ProblemLuke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson. 188-194
- Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia ProcessorWim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit. 195-201
- The Speedy DDR2 Controller For FPGAsRay Bittner. 205-211
- An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core ProcessorsAustin Rogers, Aleksandar Milenkovic. 212-218
- A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial ReconfigurationSumedha Gupta Kodipyaka, Jooheung Lee. 219-225
- High Efficiency Reconfigurable Cache for Image ProcessingZahir Larabi, Yves Mathieu, Stéphane Mancini. 226-232
- An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable HardwareAkira Yamawaki, Seiichi Serikawa, Masahiko Iwane. 233-239
- Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA DevicesAndrea Abba, Antonio Manenti, Andrea Suardi, Angelo Geraci, Giancarlo Ripamonti. 240-246
- High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient MethodAndrea Suardi, Antonio Manenti, Andrea Abba, Angelo Geraci. 247-253
- Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number GeneratorsHassan Edrees, Brian Cheung, McCullen Sandora, David B. Nummey, Deian Stefan. 254-260
- FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive ComputationMasanori Hariyama, Keita Tanji, Michitaka Kameyama. 263-266
- A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case StudyGuolei Zhu, Heng Yu, Yajun Ha, Yingmin Wang. 267-270
- A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor LogicShota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama. 271-274
- Fault Avoidance in Medium-Grain Reconfigurable Hardware ArchitecturesKylan Robinson, José G. Delgado-Frias. 275-278
- Transformable Vertexes Information based Algorithm for Online Task Placement in Reconfigurable SystemGuojun Dai, Peng Liu, Y. Fun Hu, Geyong Min, Zhigang Gao. 279-282
- A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor ArrayYoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano. 283-286
- FPGA-architecture for Knowledge-Based Target Detection in Radar Signal ProcessingSantos Lépez-Estrada, René Cumplido. 287-290
- Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU ArraysHasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. 291-294
- Nanocomputing Block based Multi-Context FPGAWeisheng Zhao, Christian Gamrat, Yves Lhuillier. 297-298
- Optimizing the FPGA Memory Design for a Sobel Edge DetectorCraig Moore, Harald Devos, Dirk Stroobandt. 299-300
- High-Level Exploration for Dynamic Reconfiguration ManagementSébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet. 301-302
- An FPGA Implementation of an Elliptic Curve Cryptosystem Coprocessor over Prime FieldsQian Ding, William Robinson. 303-304
- A Multi-Context Programmable Optically Reconfigurable Gate ArrayShinya Kubota, Minoru Watanabe. 305-306
- Optically Reconfigurable Gate Array with a One-Time Writable Holographic MemoryTakayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara. 307-308
- Lost in Space! Quantifying the Elements of FPGA SpeedupScott Sirowy, Alessandro Forin. 311-314
- Improved gradient-based motion estimation on reconfigurable platformsGuillermo Botella Juan, Uwe Meyer-Bäse, Antonio GarcÃa RÃos, LuÃs Parrilla Roure. 315-318
- Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FXMariusz Grad, Christian Plessl. 319-322
- Data path Configuration Time Reduction for Run-time Reconfigurable SystemsMahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabeghi, Koen L. M. Bertels, Georgi Gaydadjiev. 323-327
- Area Evaluation for Parallel Execution in Reconfigurable Processor ArchitecturesJorge Ortiz. 328-331
- Alignment compensation method for an optically reconfigurable gate arrayHironobu Morita, Minoru Watanabe. 332-333