Abstract is missing.
- Innovation and Wealth Creation from TechnologyRobin Saxby. 3 [doi]
- Living with Failure: Lessons from Nature?Steve Furber. 4-8 [doi]
- Low Cost Launch-on-Shift Delay Test with Slow Scan EnableGefu Xu, Adit D. Singh. 9-14 [doi]
- Dynamic Voltage Scaling Aware Delay Fault TestingNoohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod. 15-20 [doi]
- Enhancing Delay Fault Coverage through Low Power Segmented ScanZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi. 21-28 [doi]
- Single-Event Upset Analysis and Protection in High Speed CircuitsMohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto. 29-34 [doi]
- Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative StudyMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee. 35-42 [doi]
- Minimal March Tests for Dynamic Faults in Random Access MemoriesGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian. 43-48 [doi]
- A 22n March Test for Realistic Static Linked Faults in SRAMsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 49-54 [doi]
- Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable MemoriesYu-Jen Huang, Jin-Fu Li. 55-62 [doi]
- Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic FabricsWenjing Rao, Alex Orailoglu, Ramesh Karri. 63-68 [doi]
- Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable DevicesKentaroh Katoh, Hideo Ito. 69-74 [doi]
- Fault Injection-based Reliability Evaluation of SoPCsMatteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena. 75-82 [doi]
- Retention-Aware Test Scheduling for BISTed Embedded SRAMsQiang Xu, Baosheng Wang, F. Y. Young. 83-88 [doi]
- A Transparent based Programmable Memory BISTSlimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa. 89-96 [doi]
- A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and CompareBernd Laquai, Martin Hua, Guido Schulze, Michael Braun. 97-102 [doi]
- On-Chip Time Measurement Architecture with Femtosecond Timing ResolutionMatthew Collins, Bashir M. Al-Hashimi. 103-110 [doi]
- On-Chip Test Generation Using Linear SubspacesRamashis Das, Igor L. Markov, John P. Hayes. 111-116 [doi]
- Convolutional Compactors with Variable PolynomialsArtur Pogiel, Janusz Rajski, Jerzy Tyszer. 117-122 [doi]
- Deterministic Logic BIST for Transition Fault TestingValentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers. 123-130 [doi]
- Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta ModulatorsGildas Leger, Adoración Rueda. 131-136 [doi]
- Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant CircuitsErik Schüler, Daniel Scain Farenzena, Luigi Carro. 137-144 [doi]
- Testing and Diagnosis of Power Switches in SOCsSandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez. 145-150 [doi]
- A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF ApplicationsM. Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Begueret. 151-158 [doi]
- Analogue Network of Converters : A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOCVincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell. 159-164 [doi]
- Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production TestShalabh Goyal, Abhijit Chatterjee, Mike Atia. 165-172 [doi]
- Fault Collapsing for Transition Faults Using Extended Transition FaultsIrith Pomeranz, Sudhakar M. Reddy. 173-178 [doi]
- FATE: a Functional ATPG to Traverse Unstabilized EFSMsGiuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli. 179-184 [doi]
- A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay FaultsNarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz. 185-192 [doi]
- A Low Cost Alternative Method for Harmonics Estimation in a BIST ContextVincent Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, Jean-Marie Janik, B. Agnus, Philippe Cauvet, Ph. Gandy. 193-198 [doi]
- Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance ParametersByoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham. 199-204 [doi]
- Low Cost Parametric Failure Diagnosis of RF TransceiversDonghoon Han, Shalabh Goyal, Soumendu Bhattacharya, Abhijit Chatterjee. 205-212 [doi]
- Wrapper Design for the Reuse of Networks-on-Chip as Test Access MechanismAlexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes. 213-218 [doi]
- A DFT Architecture for Asynchronous Networks-on-ChipXuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach. 219-224 [doi]
- Low-Cost Online Testing of Asynchronous HandshakesDelong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov. 225-232 [doi]
- Test-per-Clock Detection, Localization and Identification of Interconnect FaultsMichal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. 233-238 [doi]
- On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis ArchitectureFrank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz. 239-246 [doi]
- Soft-Error Rate Testing of Deep-Submicron Integrated CircuitsTino Heijmen, André Nieuwland. 247-252 [doi]
- New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG)Bill Eklow, Ben Bennetts. 253-254 [doi]