Table of Contents

• Diagnosis of Failing Scan Cells through Orthogonal Response CompactionBrady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer. 1-6 [doi]
• Improved DFT for Testing Power SwitchesS. Saqib Khursheed, Sheng Yang, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn. 7-12 [doi]
• Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power SwitchesZhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty. 13-18 [doi]
• Scan Attacks and Countermeasures in Presence of Scan Response CompactorsJean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 19-24 [doi]
• Memory Optimized Two-Stimuli INL Test Method for DAC-ADC PairsEsa Korhonen, Juha Kostamovaara. 25-32 [doi]
• Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter EstimationS. Kook, A. Banerjee, Abhijit Chatterjee. 33-38 [doi]
• A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS ImagerXuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai. 39-44 [doi]
• Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked MemoriesMottaqiallah Taouil, Said Hamdioui. 45-50 [doi]
• DfT Architecture for 3D-SICs with Multiple TowersChun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu. 51-56 [doi]
• Power Aware Post-manufacture Tuning of Analog NanocircuitsAritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee. 57-62 [doi]
• Tomographic Testing and Validation of Probabilistic CircuitsAlexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes. 63-68 [doi]
• Fault Masking and Diagnosis in Reversible CircuitsMasoud Zamani, Navid Farazmand, Mehdi Baradaran Tahoori. 69-74 [doi]
• Extraction of EVM from Transmitter System ParametersAfsaneh Nassery, Sule Ozev, Marian Verhelst, Mustapha Slamani. 75-80 [doi]
• A Mixed-Signal Test Bus and Analog BIST with Unlimited Time and Voltage ResolutionStephen K. Sunter, Aubin Roy. 81-86 [doi]
• AVF Analysis Acceleration via Hierarchical Fault PruningMichail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris. 87-92 [doi]
• Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU ProcessorHai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh. 93-98 [doi]
• Reduced ATE Interface for High Test Data CompressionDariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 99-104 [doi]
• Toggle-Based Masking Scheme for Clustered Unknown Response BitsOzgur Sinanoglu. 105-110 [doi]
• Structural In-Field Diagnosis for Random Logic CircuitsAlejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein. 111-116 [doi]
• Accelerating RTL Fault Simulation through RTL-to-TLM AbstractionNicola Bombieri, Franco Fummi, Valerio Guarnieri. 117-122 [doi]
• Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the LinksAnelise Kologeski, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt. 123-128 [doi]
• Latency Analysis for Sequential CircuitsAlexander Finder, André Sülflow, Görschwin Fey. 129-134 [doi]
• Input/Output Pad for Direct Contact and Contactless TestingMauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo, L. Perilli, Roberto Cardu, Eleonora Franchi, C. Gozzi, F. Maggioni. 135-140 [doi]
• An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment EnumerationStelios Neophytou, Kyriakos Christou, Maria K. Michael. 141-146 [doi]
• Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential CircuitsJaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara. 147-152 [doi]
• A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay TestingM. Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, E. Sanchez, M. De Carvalho, Matteo Sonza Reorda. 153-158 [doi]
• A Robust Metric for Screening Outliers from Analogue Product Manufacturing Tests ResponsesShaji Krishnan, Hans G. Kerkhoff. 159-164 [doi]
• Fast and Accurate DPPM Computation Using Model Based FilteringEnder Yilmaz, Sule Ozev. 165-170 [doi]
• Optimization of Assertion Placement in Time-Constrained Embedded SystemsViacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita. 171-176 [doi]
• Critical Fault-Based Pattern Generation for Screening SDDsFang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor. 177-182 [doi]
• Structural Test for Graceful Degradation of NoC SwitchesAtefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich. 183-188 [doi]
• On Transition Fault Diagnosis Using Multicycle At-Speed Broadside TestsIrith Pomeranz. 189-194 [doi]
• Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional FailuresHongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty. 195-200 [doi]
• Online Univariate Outlier Detection in Final Test: A Robust Rolling Horizon ApproachH. C. M. Bossers, Johann Hurink, Gerard J. M. Smit. 201 [doi]
• Timing Vulnerability Factors of Ultra Deep-sub-micron CMOSMassoud Mokhtarpour Ghahroodi, Mark Zwolinski, Rick Wong, Shi-Jie Wen. 202 [doi]
• F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPGMarie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara. 203 [doi]
• Viterbi-Based Efficient Test Data CompressionDongsoo Lee, Kaushik Roy. 204 [doi]
• Memory Test Optimization for Parasitic Bit Line Coupling in SRAMsSandra Irobi, Zaid Al-Ars, Said Hamdioui. 205 [doi]
• A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST ArchitectureIoannis Voyiatzis, Costas Efstathiou, H. Antonopoulou. 206 [doi]
• FPGA Soft Error Recovery Mechanism with Small Hardware OverheadUros Legat, Anton Biasizzo, Franc Novak. 207 [doi]
• I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated SystemsMichael Nicolaidis, Vladimir Pasca, Lorena Anghel. 208 [doi]
• A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded SystemsDhiego Silva, K. Stangherlin, Leticia Maria Veiras Bolzani, Fabian Vargas. 209 [doi]
• High-Performance Diagnostic Fault Simulation on GPUsMin Li, Michael S. Hsiao. 210 [doi]
• Dynamic Test Set Selection Using Implication-Based On-Chip DiagnosisNuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar. 211 [doi]
• A Low-Cost Emulation System for Fast Co-verification and DebugJorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini. 212 [doi]
• Revisiting Application-Dependent Test for FPGA DevicesAlessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca. 213 [doi]
• Temperature-Variation-Aware Test Pattern OptimizationTomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara. 214 [doi]
• Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case StudyRamachandran Venkatasubramanian, Doohwang Chang, Sule Ozev. 215 [doi]
• Enhancement of Clock Delay Faults TestingYoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. 216 [doi]
• Dual Edge Triggered Flip-Flops for Noise Aware DesignYukiya Miura. 217 [doi]
• On High-Quality Test Pattern Selection and ManipulationFeng Yuan, Xiao Liu, Qiang Xu. 218 [doi]
• Towards Variation-Aware Test MethodsIlia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell. 219-225 [doi]