Table of Contents

• Reducing embedded software radiation-induced failures through cache memoriesThiago Santini, Paolo Rech, Gabriel L. Nazar, Luigi Carro, Flávio Rech Wagner. 1-6 [doi]
• Verification of the decimal floating-point square root operationAmr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne. 1-2 [doi]
• Logic simulation and fault collapsing with shared structurally synthesized bddsDmitri Mironov, Raimund Ubar, Jaan Raik. 1-2 [doi]
• On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial)Marco Indaco, Paolo Prinetto, Elena I. Vatajelu. 1-10 [doi]
• Using dynamic shift to reduce test data volume in high-compression designsXijiang Lin, Mark Kassab, Janusz Rajski. 1-6 [doi]
• iBoX - Jitter based Power Supply Noise sensorMiroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot. 1-2 [doi]
• Major eras of Design for TestWalden C. Rhines. 1 [doi]
• Incremental computation of delay fault detection probability for variation-aware test generationMarcus Wagner, Hans-Joachim Wunderlich. 1-6 [doi]
• Sat-based speedpath debugging using waveformsMehdi Dehbashi, Görschwin Fey. 1-6 [doi]
• A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysisFabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis. 1-2 [doi]
• A true random number generator with on-line testabilityE. Bohl, M. Lewis, S. Gallein. 1-6 [doi]
• Secure and efficient LBIST for feedback shift register-based cryptographic systemsElena Dubrova, Mats Näslund, Göran Selander. 1-6 [doi]
• Analysis and mitigation of single event effects on flash-based FPGASLuca Sterpone, Boyang Du. 1-6 [doi]
• Diagnosis of multiple faults with highly compacted test responsesAlejandro Cook, Hans-Joachim Wunderlich. 1-6 [doi]
• Smart-hopping: Highly efficient ISA-level fault injection on real hardwareHorst Schirmeier, Lars Rademacher, Olaf Spinczyk. 1-6 [doi]
• Improving polynomial datapath debugging with HEDsSomayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi. 1-6 [doi]
• Site dependencies in a multisite testing environmentThomas Lehner, Andreas Kuhr, Michael Wahl, Rainer Bruck. 1-6 [doi]
• Two soft-error mitigation techniques for functional units of DSP processorsAlireza Rohani, Hans G. Kerkhoff. 1-6 [doi]
• M-S specification binning based on digitally coded indirect measurementsAlvaro Gómez-Pau, Luz Balado, Joan Figueras. 1-6 [doi]
• Test-mode-only scan attack using the boundary scan chainSk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri. 1-6 [doi]
• On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICsShi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng. 1-2 [doi]
• Property-checking based LBIST for improved diagnosabilitySarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao. 1-2 [doi]
• Systematic generation of diagnostic software-based self-test routines for processor componentsMario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus. 1-6 [doi]
• Triple error detection for Imai-Kamiyanagi codes based on subsyndrome computationsChristian Badack, Michael Gössel. 1-2 [doi]
• Optimization of analog fault coverage by exploiting defect-specific maskingAnthony Coyette, Georges Gielen, Ronny Vanhooren, Wim Dobbelaere. 1-6 [doi]
• A collision resistant deterministic random bit generator with fault attack detection possibilitiesE. Bohl, M. Lewis, K. Damm. 1-2 [doi]
• Analysis of cell-aware test pattern effectiveness - A case study using a 32-bit automotive microcontrollerAthul Prabhu, Vlado Vorisek, Helmut Lang, Thomas Schumann. 1-2 [doi]
• Power efficient scan testing by exploiting existing error tolerance circuitry in a designAnthi Anastasiou, Yiorgos Tsiatouhas. 1-2 [doi]
• Quantified contribution of design for manufacturing to yield at 28nmThomas Herrmann, Shobhit Malik, Sriram Madhavan. 1-6 [doi]
• Avoiding burnt probe tips: Practical solutions for testing internally regulated power suppliesRichard Swanson, Anna Wong, Suraj Ethirajan, Amitava Majumdar. 1-6 [doi]
• An off-line MDSI interconnect BIST incorporated in BS 1149.1Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi. 1-2 [doi]
• Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAsFernanda Lima Kastensmidt, Jorge Tonfat, Thiago Hanna Both, Paolo Rech, Gilson I. Wirth, Ricardo Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost. 1-2 [doi]
• Variation-aware deterministic ATPGMatthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker. 1-6 [doi]
• Model based generation of high coverage test suites for embedded systemsOrlando Ferrante, Alberto Ferrari, Marco Marazza. 1-2 [doi]
• Post-bond test of Through-Silicon Vias with open defectsRosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras. 1-6 [doi]
• Accumulator-based test-per-clock scheme for low-power on-chip application of test patternsIoannis Voyiatzis. 1-2 [doi]
• Design of low cost fault tolerant analog circuits using real-time learned error compensationSuvadeep Banerjee, Alvaro Gómez-Pau, Abhijit Chatterjee. 1-2 [doi]
• Quantitative evaluation of register vulnerabilities in RTL control pathsLiang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1-2 [doi]
• Concurrent online BIST for sequential circuits exploiting input reduction and output space compactionIoannis Voyiatzis. 1-2 [doi]
• Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiationDan Alexandrescu, Luca Sterpone, Celia López-Ongil. 1-6 [doi]
• A new efficiency criterion for security oriented error correcting codesYaara Neumeier, Osnat Keren. 1-6 [doi]
• A distance-based test cube merging procedure for compatible and incompatible test cubesIrith Pomeranz. 1-2 [doi]
• Output-bit selection with X-avoidance using multiple counters for test-response compactionWei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh. 1-6 [doi]
• Cell-aware experiences in a high-quality automotive test suiteFriedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, G. Maugard, A. Prashanthi, J. Schloeffel, Wilfried Redemund, Andreas Glowatz, A. Fast, Janusz Rajski. 1-6 [doi]
• Factoring variability in the Design/Technology Co Optimisation (DTCO) in advanced CMOSAsen Asenov. 1 [doi]
• Interleaved scrambling technique: A novel low-power security layer for cache memoriesMadalin Neagu, Liviu Miclea, Salvador Manich. 1-2 [doi]
• INL systematic reduced-test technique for Pipeline ADCsEduardo J. Peralías, Antonio Jose Ginés, Adoración Rueda. 1-6 [doi]
• GPU-based timing-aware test generation for small delay defectsKuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang. 1-2 [doi]
• Automatic correction of certain design errors using mutation techniquePayman Behnam, Bijan Alizadeh, Zainalabedin Navabi. 1-2 [doi]
• Error detection and recovery in better-than-worst-case timing designsAdit D. Singh. 1-6 [doi]
• Built-in self-calibration of CMOS-compatible thermopile sensor with on-chip electrical stimulusJia Li, Zhuolei Huang, Weibing Wang. 1-6 [doi]
• Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SICShudong Lin, Gordon W. Roberts. 1-2 [doi]
• Detection conditions for errors in self-adaptive better-than-worst-case designsIlia Polian, Jie Jiang, Adit D. Singh. 1-6 [doi]
• Shadow-scan design with low latency overhead and in-situ slack-time monitoringSébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman. 1-6 [doi]
• Homogeneous many-core processor system test distribution and execution mechanismArezoo Kamran, Zainalabedin Navabi. 1-2 [doi]
• Reconfigurable high performance architectures: How much are they ready for safety-critical applications?Davide Sabena, Luca Sterpone, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robért Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer. 1-8 [doi]
• Optimization-based multiple target test generation for highly compacted test setsStephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler. 1-6 [doi]
• A novel adaptive fault tolerant flip-flop architecture based on TMRLuca Cassano, Alberto Bosio, Giorgio Di Natale. 1-2 [doi]