Abstract is missing.
- Generation of embedded RAMs with built-in test using object-oriented programmingMichael Zimmermann, Manfred Geilert. 2-6 [doi]
- ASTA: an integrated system for bist analysis & automatic test generationSteve Hodgson, Len Theobald, W. B. Hughes, Richard Illman. 7-12 [doi]
- Tools and devices supporting the pseudo-exhaustive testSybille Hellebrand, Hans-Joachim Wunderlich. 13-17 [doi]
- Development of test programs with the aid of a testeroriented pattern languageMartin Klimke, Christian Winkelmeyr, Herbert Eichinger. 18-22 [doi]
- A database interface for phased tool integrationThomas Kathöfer, W. Fox, D. Nolte, K. Pielsticker, R. Quester, F. Rupprecht, M. Schrewe. 24-28 [doi]
- On the architecture of a CAD framework: the NELSIS approachPieter van der Wolf, Peter Bingley, Patrick Dewilde. 29-33 [doi]
- Design data management in a distributed hardware environmentG. W. Sloof, Peter Bingley, Patrick Dewilde, T. G. R. van Leuken, Pieter van der Wolf. 34-38 [doi]
- The NMP-CADLAB framework: a common framework for tool integration and developmentJaan Haabma, Bernd Steinmueller. 39-43 [doi]
- On the notion of the normal form register-level structures and its applications in design-space explorationRanga Vemuri. 46-51 [doi]
- Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction levelHélène Collavizza. 52-56 [doi]
- Formal boolean manipulations for the verification of sequential machinesOlivier Coudert, Christian Berthet, Jean Christophe Madre. 57-61 [doi]
- Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environmentDiederik Verkest, Luc J. M. Claesen, Hugo De Man. 62-66 [doi]
- Synthesis of delay functions in DSP compilersA. Delaruelle, O. McArdle, Jef L. van Meerbergen, C. Niessen. 68-72 [doi]
- A branch-and-bound method for optimal transformation of data flow graphs for observing hardware constraintsWerner Grass. 73-77 [doi]
- SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis systemNeerav Berry, Barry M. Pangrle. 78-82 [doi]
- A new approach to pipeline optimisationDavid J. Mallon, Peter B. Denyer. 83-88 [doi]
- NETHDL: abstraction of schematics to high-level HDLDaniel Fischer, Yossi Levhari, Gadi Singer. 90-96 [doi]
- Comparison of implementations of real arithmetic in ELLA and VHDLC. O. Newton, M. G. Hill. 97-101 [doi]
- MINT: a VHDL simulation systemMart Altmäe. 102-106 [doi]
- Structured analysis and VHDL in embedded ASIC design and verificationTuomo Tikkanen, Timo Lappänen, Jorma Kivelä. 107-111 [doi]
- An algebraic model for design space with applications to function module generationAkhilesh Tyagi. 114-118 [doi]
- Transistor placement and interconnect algorithms for leaf cell synthesisMartin Lefebvre, Chong Chan, Grant Martin. 119-123 [doi]
- A flexible hierarchical 3-D module assemblerRobi Dutta, Maurice Marks, Craig Morrissey, Ravi Rao, Lee Sapiro. 124-128 [doi]
- PARAGON: a new package for gate matrix layout synthesisR. Burgess, C. Wouters. 129-134 [doi]
- A neural net based self organising scheduling algorithmAhmed Hemani, Adam Postula. 136-140 [doi]
- Interconnect optimisation during data path allocationL. Stok. 141-145 [doi]
- Matching system and component behaviour in MIMOLA synthesis toolsPeter Marwedel. 146-156 [doi]
- Redesign using state splittingRaul Camposano, Reinaldo A. Bergamaschi. 157-161 [doi]
- Silicon compilation of switched: capacitor networksMehrdad Negahban, Daniel Gajski. 164-168 [doi]
- An intelligent design system for analogue integrated circuitsGeorges G. E. Gielen, Koen Swings, Willy M. C. Sansen. 169-173 [doi]
- A graphical system for hierarchical specifications and checkups of VLSI circuitsBernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann. 174-179 [doi]
- Automatic knowledge acquisition in a digital circuit design systemJung-Gen Wu. 180-184 [doi]
- Optimal via-shifting in channel compactionYang Cai, D. F. Wong. 186-190 [doi]
- Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear regionChong-Min Kyung, Josef Widder, Dieter A. Mlynski. 191-195 [doi]
- An efficient two-dimensional compaction algorithm for VLSI symbolic layoutShao-Jun Wei, Jacques Leroy, Raymond Crappe. 196-200 [doi]
- CACTUS: a symbolic CMOS two-dimensional compactorTomás Pérez Segovia, Anne-Françoise Joanblanq. 201-205 [doi]
- An iterative algorithm for the binate covering problemM. Pipponzi, Fabio Somenzi. 208-211 [doi]
- Technology mapping using boolean matching and don t care setsFrederic Mailhot, Giovanni De Micheli. 212-216 [doi]
- Gate sizing in MOS digital circuits with linear programmingMichel R. C. M. Berkelaar, Jochen A. G. Jess. 217-221 [doi]
- A new synthesis technique for multilevel combinational circuitsLiliana Díaz-Olavarrieta, Safwat G. Zaky. 222-227 [doi]
- An event-driven transient simulation algorithm for MOS and bipolar circuitsD. Patrick, C. Lyden. 230-234 [doi]
- PLATO: a new piecewise linear simulation toolM. T. van Stiphout, Jos T. J. van Eijndhoven, H. W. Buurman. 235-239 [doi]
- Event-driven behavioural simulation of analogue transfer functionsR. A. Cottrell. 240-243 [doi]
- A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulationPatrick Odent, Luc J. M. Claesen, Hugo De Man. 244-248 [doi]
- CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISPChristian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers. 250-256 [doi]
- A VLSI floorplanner based on balloon expansionNoritake Yonezawa, Nobuyuki Nishiguchi, Atsushi Etani, Fumiaki Tsukuda, Ryuichi Hashishita. 257-261 [doi]
- A system for floorplanning with hierarchical placement and wiringKevin McCullen, John Thorvaldson, David Demaris, Patrick Lampin. 262-265 [doi]
- ACCORDO: second generation floor planningGrazia Arato, Giuseppe Bussolino, Anna M. Fiammengo, Roberto Manione. 266-270 [doi]
- Open-ended system for high-level synthesis of flexible signal processorsDirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man. 272-276 [doi]
- System synthesis using behavioural descriptionsHeinrich Krämer, Wolfgang Rosenstiel. 277-282 [doi]
- Towards a global solution to high level synthesis problemsAbdelhakim Safir, Bertrand Zavidovique. 283-288 [doi]
- The EVE companion simulatorDaniel K. Beece, R. Damiano, Georgina Papp, R. Schoen. 290-295 [doi]
- An incremental functional simulator implemented on a network of transputersKeith Dimond, Samir Hassan. 296-300 [doi]
- Derivation of signal flow for switch-level simulationDavid T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham. 301-305 [doi]
- Multirate integration in a direct simulation methodJos T. J. van Eijndhoven, M. T. van Stiphout, H. W. Buurman. 306-311 [doi]
- An efficient placement method for large standard-cell and sea-of-gates designsH. J. Kappen, F. M. J. de Bont. 312-316 [doi]
- VLSI: placement based on routing and timing informationJörn Garbers, Bernhard Korte, Hans Jürgen Prömel, E. Schwietzke, Angelika Steger. 317-321 [doi]
- Optimal slicing of plane point placementsLukas P. P. P. van Ginneken, Ralph H. J. M. Otten. 322-326 [doi]
- A gate-matrix oriented partitioning approach for multilevel logical networksFrank H. Huentemann, Utz G. Baitinger. 327-331 [doi]
- On the fault coverage of delay fault detecting testsAnkan K. Pramanick, Sudhakar M. Reddy. 334-338 [doi]
- Some relationships between delay testing and stuck-open testing in CMOS circuitsRene David, S. Rahal, J. L. Rainard. 339-343 [doi]
- Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networksF. Darlay, B. Courtois. 344-349 [doi]
- Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoringNiraj K. Jha, Qiao Tong. 350-354 [doi]
- A data-structuring technique for gridded VLSI layoutsSaleem M. Haider, Peng H. Ang. 356-362 [doi]
- An object-oriented persistent database interface for CADM. N. Sim, P. M. Dewilde. 363-367 [doi]
- Design management within a design environmentPetra Drescher, Julia Miller, Gerhard Schulz. 368-373 [doi]
- A design representation for high level synthesisMikael R. K. Patel. 374-379 [doi]
- Hierarchical layout verification for submicron designsW. Meier. 382-386 [doi]
- CIRCE: a program for parasitic parameter extractionCarlo Marazzini, Mauro Santomauro, Michele Taliercio. 387-390 [doi]
- An improved layout verification algorithm (LAVA)Magdy S. Abadir, Jack Ferguson. 391-395 [doi]
- Simulation based verification of register-transfer level behavioral synthesis toolsR. Ernst, S. Sutarwala, J.-Y. Jou, M. Tong. 396-400 [doi]
- A new switch-level test pattern generation algorithm based on single path over a graph representationCarles Ferrer, Joan Oliver, Elena Valderrama. 402-406 [doi]
- Fault modelling and fault equivalence in CMOS technologyMarie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch. 407-412 [doi]
- A strategy for testability enhancement at layout levelJoão Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves, R. Crespo. 413-417 [doi]
- Accelerated test pattern generation by cone-oriented circuit partitioningTorsten Grüning, Udo Mahlstedt, Wilfried Daehn, Cengiz Özcan. 418-421 [doi]
- Economics of point accellerationEric William Burger, Guido Dedene. 424-428 [doi]
- Logic optimization on a concurrent processing computerF. Theeuwen. 429-433 [doi]
- The use of computer-aided software engineering technology in systems and software designD. F. Burrows. 434-438 [doi]
- Rapid prototyping using high density interconnectsRichard I. Hartley, Kenneth Welles II, Michael Hartman, Paul Delano, Abhijit Chatterjee. 439-443 [doi]
- MOLE: a sea-of-gates detailed routerArvind Srinivasan, Ernest S. Kuh. 446-450 [doi]
- Channel routing with non-terminal doglegsBryan Preas. 451-458 [doi]
- On the k-layer planar subset and via minimization problemsJason Cong, C. L. Liu. 459-463 [doi]
- Path search on rectangular floorplanChang-Sheng Ying, Joshua Sook-Leung Wong, X. L. Hong, E. Q. Wang. 464-468 [doi]
- Diagnosis oriented test pattern generationPaolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda. 470-474 [doi]
- PROOFS: a super fast fault simulator for sequential circuitsWu-Tung Cheng, Janak H. Patel. 475-479 [doi]
- High level test generation using data flow descriptionsKaushik Roy, Jacob A. Abraham. 480-484 [doi]
- Experience in functional-level test generation and fault coverage in a silicon compilerChristian Jay. 485-490 [doi]
- SPI: an open interface integrating highly interactive electronic CAD toolsJ. P. Schupp, Johan Cockx, Luc J. M. Claesen, Hugo De Man. 492-495 [doi]
- A procedural interface to CAD data based on EDIFT. C. O. Young, H. J. Kahn. 496-500 [doi]
- Ghost/Spook: user interface and process management in the PACE frameworkPedro Reis dos Santos, Helena Sarmento, Luís M. Vidigal. 501-505 [doi]
- Storage mechanism for VHDL intermediate formBruno Poterie. 506-510 [doi]
- Formal verification of timing conditionsHans Eveking, Christoph Mai. 512-517 [doi]
- SLOCOP-II: a versatile timing verification system for MOSVLSIP. Johannes, P. Das, Luc J. M. Claesen, Hugo De Man. 518-523 [doi]
- Automatic generation of timing specifications for CMOS transistor subnetworksRobert Tjärnström. 524-528 [doi]
- Path runner: an accurate and fast timing analyserDenis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne. 529-533 [doi]
- Efficent suboptimal state assignment for large sequential machinesLech Józwiak. 536-541 [doi]
- Multi-level synthesis on PALsGabriele Saucier, Pascal Sicard, Laurent Bouchet. 542-546 [doi]
- State assignment of controllers for optimal area implementationGabriele Saucier, Christopher Duff, Franck Poirot. 547-551 [doi]
- A new method for the state reduction of incompletely specified finite sequential machinesMaria J. Avedillo, José M. Quintana, José Luis Huertas. 552-556 [doi]
- Transmission gate delay models for circuit optimizationVeronika Eisele, Bernhard Hoppe, Oliver Kiehl. 558-562 [doi]
- An accurate model for ambiguity delay simulationThomas H. Krodel, Kurt Antreich. 563-567 [doi]
- Switch-level timing models in the MOS simulator BRASILH. Warmers, D. Sass, Ernst-Helmut Horneber. 568-572 [doi]
- Software architecture of universal hardware modelerNorman F. Kelly, Holly E. Stump. 573-577 [doi]
- Design to test migration: a tester and a simulatorGordon F. Taylor. 578-582 [doi]
- Solution of a module orientation and rotation problemXianjin Yao, C. L. Liu. 584-588 [doi]
- A new algorithm for transistor sizing in CMOS circuitsAllen C.-H. Wu, Nels Vander Zanden, Daniel Gajski. 589-593 [doi]
- Cell based performance optimization of combinational circuitsUwe Hinsberger, Reiner Kolla. 594-599 [doi]
- A dynamic programming approach to the power supply net sizing problemReiner Kolla. 600-604 [doi]
- NAUTILE: a safe environment for silicon compilationP. Bondono, Ahmed Amine Jerraya, A. Hornik, Bernard Courtois, D. Bonifas. 605-609 [doi]
- An architecture for synthesis of testable finite state machinesVishwani D. Agrawal, Kwang-Ting Cheng. 612-616 [doi]
- CGE: automatic generation of controllers in the CATHEDRAL-II silicon compilerJ. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man. 617-621 [doi]
- Fuzzy specification of finite state machinesSiegfried I. Mensch, Hans Martin Lipp. 622-626 [doi]
- The effectiveness of different test sets for PLAsPeter C. Maxwell, Hans-Joachim Wunderlich. 628-632 [doi]
- Fully testable PLA design with minimal extra inputChe W. Chiou, Ted. C. Yang. 633-638 [doi]
- PEST: a tool for implementing pseudo-exhaustive self testEleanor Wu, Paul W. Rutkowski. 639-643 [doi]
- Design for verification testabilityAndrzej Krasniewski. 644-648 [doi]
- Pre-placement of VLSI blocks through learning neural networksDaniele D. Caviglia, Giacomo M. Bisio, Francesco Curatelli, L. Giovannacci, Luigi Raffo. 650-654 [doi]
- Fuzzy set based initial placement for IC layoutM. Razaz, J. Gan. 655-659 [doi]
- GASP: a Genetic Algorithm for Standard cell PlacementKhushro Shahookar, Pinaki Mazumder. 660-664 [doi]
- A new clustering approach and its application to BBL placementM. Y. Yu, X. L. Hong, Y. E. Lien, Z. Z. Ma, J. G. Bo, W. J. Zhuang. 665-669 [doi]