Table of Contents

• Device selection for system partitioningUlrich Weinmann, Oliver Bringmann, Wolfgang Rosenstiel. 2-7 [doi]
• A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemesMarkus Schwiegershausen, Peter Pirsch. 8-13 [doi]
• KANDIS - a tool for construction of mixed analog/digital systemsPeter Oehler, Christoph Grimm, Klaus Waldschmidt. 14-19 [doi]
• Information model of a compound graph representation for system and architecture level designPeter Conradi. 22-27 [doi]
• A core information model of VHDLCristian A. Giumale, Hilary J. Kahn. 28-33 [doi]
• Practical inter-operation of CAD tools using a flexible procedural interfaceZahir Moosa, Nick Filer, Michael Brown, J. Heaton, J. Pye. 34-39 [doi]
• An approach for classification of integrated circuits by a knowledge conserving library conceptD. Wagenblasst, Wolfgang Thronicke. 40-45 [doi]
• Timing optimization by bit-level arithmetic transformationsLuc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man. 48-53 [doi]
• Exploiting power-up delay for sequential optimizationVigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton. 54-59 [doi]
• Tree restructuring approach to mapping problem in cellular-architecture FPGAsNaveen Ramineni, Malgorzata Chrzanowska-Jeske, Naveen Buddi. 60-65 [doi]
• Generating several solutions for the scheduling problem in high-level synthesisHans Achatz. 66-71 [doi]
• Post routing performance optimization via tapered link insertion and wiresizingTianxiong Xue, Ernest S. Kuh. 74-79 [doi]
• Performance-oriented placement and routing for field-programmable gate arraysMichael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins. 80-85 [doi]
• Layout synthesis for datapath designsNaveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe. 86-90 [doi]
• An investigation of iterative routing algorithmsZahir Moosa, Douglas Edwards. 91-96 [doi]
• Bottleneck removal algorithm for dynamic compaction and test cycles reductionSrimat T. Chakradhar, Anand Raghunathan. 98-104 [doi]
• On generating compact test sequences for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. 105-110 [doi]
• Partial scan selection for user-specified fault coverageClay Gloster, Franc Brglez. 111-116 [doi]
• Testable synthesis of high complex control devicesFranco Fummi, U. Rovati, Donatella Sciuto. 117-122 [doi]
• A memory selection algorithm for high-performance pipelinesSmita Bakshi, Daniel D. Gajski. 124-129 [doi]
• Area efficient DSP datapath synthesisAndrew A. Duncan, David C. Hendry. 130-135 [doi]
• Metric-based transformations for self testable VLSI designs with high test concurrencyMahsa Vahidi, Alex Orailoglu. 136-141 [doi]
• On implementation choices for iterative improvement partitioning algorithmsLars W. Hagen, Dennis J.-H. Huang, Andrew B. Kahng. 144-149 [doi]
• Multiway netlist partitioning onto FPGA-based board architectureUlrike Ober, Manfred Glesner. 150-155 [doi]
• Timing influenced force directed floorplanningHabib Youssef, Sadiq M. Sait, Khalid J. Al-Farra. 156-161 [doi]
• Scalable performance scheduling for hardware-software cosynthesisThomas Benner, Rolf Ernst, Achim Österling. 164-169 [doi]
• Cosimulation of real-time control systemsJuha-Pekka Soininen, Tuomo Huttunen, Kari Tiensyrjä, Hannu Heusala. 170-175 [doi]
• A hardware/software partitioning algorithm for pipelined instruction set processorBinh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi. 176-181 [doi]
• A unified approach to the extraction of realistic multiple bridging and break faultsGerald Spiegel, Albrecht P. Stroele. 184-189 [doi]
• Fault modeling of differential ECLUdo Jorczyk, Wilfried Daehn, Oliver Neumann. 190-195 [doi]
• Quality considerations in delay fault testingAlicja Pierzynska, Slawomir Pilarski. 196-201 [doi]
• Path delay ATPG for standard scan designHannes C. Wittmann, Manfred Henftling. 202-207 [doi]
• Path sensitization of combinational circuits and its impact on clocking of sequential systemsRafael Peset Llopis. 210-215 [doi]
• Delay modelling improvement for low voltage applicationsJean Michel Daga, Michel Robert, Daniel Auvergne. 216-221 [doi]
• Functional-level analog macromodeling with piecewise linear signalsJerzy Dabrowski. 222-227 [doi]
• FOGBUSTER: an efficient algorithm for sequential test generationUwe Gläser, Heinrich Theodor Vierhaus. 230-235 [doi]
• An adaptive distributed algorithm for sequential circuit test generationJames Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal. 236-241 [doi]
• Search space reduction through clustering in test generationZohair Sahraoui, Paul Six, Ivo Bolsens, Hugo De Man. 242-247 [doi]
• A formal non-heuristic ATPG approachManfred Henftling, Hannes C. Wittmann, Kurt Antreich. 248-253 [doi]
• Debugging of behavioral VHDL specifications by source level emulationGernot Koch, Udo Kebschull, Wolfgang Rosenstiel. 256-261 [doi]
• A backplane approach for cosimulation in high-level system specification environmentsS. Schmerler, Y. Tanurhan, Klaus D. Müller-Glaser. 262-267 [doi]
• Integration of VHDL into a system design environmentLudwig Schwoerer, Matthias Lück, Hartmut Schröder. 268-273 [doi]
• An improved relaxation approach for mixed system analysis with several simulation toolsVladimir B. Dmitriev-Zdorov, Bernhard Klaassen. 274-279 [doi]
• Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs)Theodore Karoubalis, George Alexiou, Nick Kanopoulos. 282-287 [doi]
• Computing subsets of equivalence classes for large FSMsGianpiero Cabodi, Stefano Quer, Paolo Camurati. 288-293 [doi]
• Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functionsEnrico Macii, Massimo Poncino. 294-299 [doi]
• Model of conceptual design of complex electronic systemsAlexander N. Soloviev, Alexander L. Stempkovsky. 302-307 [doi]
• Cooperative concurrency control for design environmentsAnsgar Bredenfeld. 308-313 [doi]
• Reduced design time by load distribution with CAD framework methodology informationJürgen Schubert, Arno Kunzmann, Wolfgang Rosenstiel. 314-319 [doi]
• System modeling, hardware-software codesign, and mixed modeling with hardware description languageSidharta Mohanty, Philip A. Wilsey. 322-327 [doi]
• Closeness metrics for system-level functional partitioningFrank Vahid, Daniel D. Gajski. 328-333 [doi]
• Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systemsSanthanam Srinivasan, Niraj K. Jha. 334-339 [doi]
• Performance-complexity analysis in hardware-software codesign for real-time systemsVictor V. Toporkov. 340-345 [doi]
• Mesh current method for computing the current distribution in planar conductor surfaces and possible applications in circuit simulationArmin Englmaier. 348-353 [doi]
• Prediction of radiated electromagnetic emissions from PCB traces based on green dyadicsE. Leroux, Flavio G. Canavero, G. Vecchi. 354-359 [doi]
• Software system for semiconductor devices, monolith and hybrid ICs thermal analysisKonstantin O. Petrosjanc, I. A. Kharitonov, N. I. Rybov, Peter P. Maltcev. 360-365 [doi]
• An approach to guided incremental specificationThomas Gabler, Sabine März-Rössel. 368-373 [doi]
• Semi-dynamic scheduling of synchronization-mechanismsWolfgang Ecker. 374-379 [doi]
• A design system for special purpose processors based on architectures for distributed processingKatsuhiko Shirai, Jin Hiwatashi. 380-385 [doi]
• Formulation and evaluation of scheduling techniques for control flow graphsMaher Rahmouni, Ahmed Amine Jerraya. 386-391 [doi]
• A high performance VHDL simulator for large systems designSteve Hodgson, Zak Shaar, Andy Smith. 394-399 [doi]
• Use of embedded scheduling to compile VHDL for effective parallel simulationJohn Willis, Zhiyuan Li, Tsang-Puu Lin. 400-405 [doi]
• Latest benchmark results of VHDL simulation systemsEugen Röhm. 406-411 [doi]
• Towards verifying VHDL descriptions of processorsLaurent Arditi, Hélène Collavizza. 414-419 [doi]
• A native process algebra for VHDLPeter T. Breuer, Natividad Martínez Madrid. 420-426 [doi]
• Inheritance concept for signals in object-oriented extensions to VHDLGuido Schumacher, Wolfgang Nebel. 428-435 [doi]
• Object-oriented high-level modeling of system components for the generation of VHDL codeKarlheinz Agsteiner, Dieter Monjau, Sören Schulze. 436-441 [doi]
• High-level synthesis and codesign methods: an application to a videophone codecPierre G. Paulin, Jean Fréhel, Michel Harrand, Elisabeth Berrebi, Clifford Liem, François Naçabal, Jean-Claude Herluison. 444-451 [doi]
• Timing constraint specification and synthesis in behavioral VHDLPetru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli. 452-457 [doi]
• VHDL-based communication and synchronization synthesisWolfgang Ecker, Manfred Huber. 458-462 [doi]
• A reuse scenario for the VHDL-based hardware design flowViktor Preis, Renate Henftling, Markus Schütz, Sabine März-Rössel. 464-469 [doi]
• VHDL based design methodology for hierarchy and component re-usePolen Kission, Hong Ding, Ahmed Amine Jerraya. 470-475 [doi]
• Quantifying design productivity: an effort distribution analysisMakarand Joshi, Hideaki Kobayashi. 476-481 [doi]
• VHDL quality: synthesizability, complexity and efficiency evaluationM. Mastretti. 482-487 [doi]
• Design and use of a system-level specification and verification methodologyM. M. Kamal Hashmi, Alistair C. Bruce. 490-495 [doi]
• Design management requirements for hardware description languagesFlávio Rech Wagner. 496-501 [doi]
• An effective system development environment based on VHDL prototypingSerafín Olcoz, Luis Entrena, Luis Berrojo. 502-507 [doi]
• Procedure exlining: a new system-level specification transformationFrank Vahid. 508-513 [doi]
• LibQA—library quality assurance for VHDL synthesis and simulationRonald B. Stewart. 516-521 [doi]
• Generating VHDL-A—like models using ABSynthVincent Moser, Hans Peter Amann, Pascal Nussbaum, Fausto Pellandini. 522-527 [doi]
• VHDL package for description of fuzzy logic controllersD. Galán, Carlos J. Jiménez, Angel Barriga Barrios, Santiago Sánchez-Solano. 528-533 [doi]
• A classification of design steps and their verificationWolfgang Ecker. 536-541 [doi]
• Verification of a production cell using an automatic verification environment for VHDLRonald Herrmann, Thomas Reielts. 542-547 [doi]
• Verification of a production cell controller using symbolic timing diagramsRainer Schlör, Franz Korf. 548-553 [doi]
• How to efficiently build VHDL testbenchesMarkus Schütz. 554-559 [doi]
• A DSP ASIC design flow based on VHDL and ASIC-emulationJan Andersson. 562-567 [doi]
• System level design, a VHDL based approachJoris van den Hurk, Edwin Dilling. 568-573 [doi]
• Setting up a retrieval system for design reuse—experiences and acceptanceGerhard H. Büttner. 575-578 [doi]
• The VHDL based design of the MIDA MPEG1 audio decoderAndrea Finotello, Maurizio Paolini. 579-584 [doi]
• Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionicsM. Romdhani, P. Chambert, A. Jeffroy, P. de Chazelles, Ahmed Amine Jerraya. 585-590 [doi]
• Issues in low-power design for telecomPaul Vanoostende, Geert van Wauwe. 591-593 [doi]
• Creating hierarchy in HDL-based high density FGPA designCarol A. Fields. 594-599 [doi]
• ODE: output direct state machine encodingJ. Forrest. 600-605 [doi]