Table of Contents

• Keynote Speech: Design Testing and Evaluation Techniques for Software Reliability EngineeringMichael R. Lyu. [doi]
• Some Research Projects on Clusters of Personal ComputersGiovanni Chiola. [doi]
• Solving Synthesis Problems with Genetic AlgorithmsLech Józwiak, Niek Ederveen, Adam Postula. 10001-10007 [doi]
• Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship MeasureMariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki. 10008-10015 [doi]
• An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound VariablesMichael Burns, Marek A. Perkowski, Lech Józwiak. 10016-10023 [doi]
• A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis ToolHenry Selvaraj, Muthukumar Venkatesan. 10024 [doi]
• Design Correctness of Digital SystemsCorrie Huijs. 10030-10033 [doi]
• Performing High-Level Synthesis via Program Transformations within a Theorem ProverChristian Blumenröhr, Dirk Eisenbiegler. 10034-10037 [doi]
• Specification of Exception Handling in Grammar-Based Hardware SynthesisJohnny Öberg, Anshul Kumar, Ahmed Hemani. 10038-10041 [doi]
• Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard Hardware Description LanguagesA. C. Verschueren. 10042-1045 [doi]
• Verification of Embedded Real-Time Systems Using Hardware/Software CosimulationMohammed El Shobaki. 10046-10050 [doi]
• Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a ChipDenis Hommais, Frédéric Pétrot. 10051-10054 [doi]
• Grammar Based Modelling and Synthesis of Device Drivers and Bus InterfacesMattias O Nils, Johnny Öberg, Axel Jantsch. 10055-10058 [doi]
• Optimal System-Level Synthesis of Digital Systems for Real-Time ApplicationsArmin Bender. 10059-10064 [doi]
• A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software CodesignJesper Grode, Jan Madsen. 10065-10069 [doi]
• A FPGA Implementation of a Video Rate Multi-Target Tracking SystemJoan Aranda, Joan Climent, Antoni Grau. 10070 [doi]
• An Approach to High-Level Synthesis Using Constraint Logic ProgrammingKrzysztof Kuchcinski. 10074-10082 [doi]
• Operation Binding and Scheduling for Low Power Using Constraint Logic ProgrammingFlavius Gruian, Krzysztof Kuchcinski. 10083-10090 [doi]
• Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis EnvironmentGeorge Economakos, George K. Papakonstantinou. 10091-10098 [doi]
• Register Allocation with Simultaneous BIST IntrusioKatzalin Olcoz, Francisco Tirado. 10099-10106 [doi]
• An Improved Register-Transfer Level Functional Partitioning Approach for TestabilityLaurence Tianruo Yang, Zebo Peng. 10107 [doi]
• Automated Synthesis of Interleaved Memory Systems for Custom Computing MachineAdam Postula, Song Chen, Lech Józwiak, David Abramson. 10115-10122 [doi]
• Image Convolution on FPGAs: The Implementation of a Multi-FPGA FIFO StructureArrigo Benedetti, Andrea Prati, Nello Scarabottolo. 10123-10130 [doi]
• Pipeline Architecture of Specialized Reconfigurable Processors in FPGA Structures for Real-Time Image Pre-ProcessingKazimierz Wiatr. 10131-10138 [doi]
• Arithmetic Image Coding/Decoding Architecture Based on a Cache MemoryRoberto R. Osorio, Montserrat Bóo, Javier D. Bruguera. 10139 [doi]
• Hardware Architecture Modelling Using an Object-Oriented MethodFrédéric Mallet, Fernand Boéri, Jean-François Duboc. 10147-10153 [doi]
• System Level Modelling for Hardware/Software SystemsJeroen Voeten, P. H. A. van der Putten, Marc Geilen, M. P. J. Stevens. 10154-10161 [doi]
• Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney IIIDiego C. Ruspini, Oussama Khatib, Giovanni De Micheli. 10162-10167 [doi]
• Process Scheduling for Performance Estimation and Synthesis of Hardware/Software SystemsPetru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop. 10168 [doi]
• Minimization of Algorithmic State MachinesSamary Baranov. 10176-10179 [doi]
• How Faults can be Simulated in Self-Testable VLSI Digital CircuitsDariusz Bojanowicz. 10180-10183 [doi]
• Experimental Evaluation of Pseudorandom Test EffectivenessJanusz Sosnowski. 10184-10187 [doi]
• Entropy-Based Design of Low Power FSMsLilia Kashirova, Olga Tveretina. 10188-10191 [doi]
• RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global RoutingJuan de Vicente, Juan Lanchares, Román Hermida. 10192-10195 [doi]
• Modified Approach to Automata State Encoding for LUT FPGA ImplementationIgor Lemberski. 10196-10199 [doi]
• Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAsValery Sklyarov, Nuno Lau, Ricardo Sal Monteiro, Andreia Melo, Arnaldo Oliveira, Konstantin Kondratjuk. 10200-10203 [doi]
• The Impact of Area Optimization for the Power Consumption of ControllersH.-Ch. Dahmen, Uwe Gläser. 10204-10207 [doi]
• Extending a Monoprocessor Real-Time System in a Multiprocessing Environment, DSP-BasedS. Aiello, Antonio Anzalone, M. Bartolucci, G. Cardella, S. Cavallaro, E. De Filippo, S. Femino, C. Garusi, M. Geraci, Francesco Giustolisi, Paolo Guazzoni, M. Iacono Manno, G. Lanzalone, G. Lanzano, S. Lo Nigro, G. Manfredi, A. Pagano, M. Papa, S. Pirrone, G. Politi, F. Porto, F. Rizzo, S. Sambataro, G. Savino, L. Sperduto, C. Sutera, Luisa Zetta. 10208-10211 [doi]
• A Useful Micropipeline Architecture to Implement DSP AlgorithmsOliver Chiu-sing Choy, Tin-chak Pang, Juraj Povazanec, Cheong-fat Chan. 10212 [doi]
• Control System for a Low Energy Particle DetectorS. Sánchez, Daniel Meziat, M. Carbajo, J. Medina, E. Bronchalo, J. Rodríguez-Pacheco, L. del Pera. 10216-10220 [doi]
• DELFT-JAVA Link Translation BufferC. John Glossner, Stamatis Vassiliadis. 10221 [doi]
• Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic ProgrammingEduard Cerny, Fen Jin. 10229-10236 [doi]
• Rate Assignment for Embedded Reactive Real-Time SystemsYoungsoo Shin, Kiyoung Choi. 10237 [doi]
• Hardware to Software Migration with Real-Time Thread IntegrationAlexander G. Dean, John Paul Shen. 10243 [doi]
• Design of Self-Synchronized Component FSMs for Self-Timed SystemsLoc Bao Nguen, Marek A. Perkowski, Lech Józwiak. 10253-10260 [doi]
• Multi-Criterial State Assignment for Low Power FSM DesignManfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske. 10261-10268 [doi]
• A New Approach to And/Or/Exor Factorization for Regular ArrayNing Song, Marek A. Perkowski. 10269 [doi]
• On the Design Complexity of the Issue Logic of Superscalar MachinesSorin Cotofana, Stamatis Vassiliadis. 10277-10284 [doi]
• Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction ReissueToshinori Sato. 10285-10292 [doi]
• The Latency Hiding Effectiveness of Decoupled Access/Execute ProcessorsJoan-Manuel Parcerisa, Antonio González. 10293-10300 [doi]
• Revolver: A High-Performance MIMD Architecture for Collision Free ComputingJohnny Öberg, Peeter Ellervee. 10301 [doi]
• A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign ProcesJ. A. Maestro, Daniel Mozos, Julio Septién. 10309-10312 [doi]
• Hierarchical Conditional Dependency Graphs for Conditional Resource SharingApostolos A. Kountouris, Christophe Wolinski. 10313-10316 [doi]
• Formal Extraction of Memorizing Elements for Sequential VHDL SynthesisLudovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa. 10317-10620 [doi]
• Data Speculative Multithreaded ArchitecturePedro Marcuello, Antonio González. 10321-10324 [doi]
• The Impact of a Realistic Cache Structure on a Statically Scheduled ArchitectureDaniel Tate, Gordon Steven, Paul Findlay. 10325-10328 [doi]
• How to Half the Latency of IEEE Compliant Floating-Point MultiplicationPeter-Michael Seidel. 10329-10332 [doi]
• Impact of Reducing Miss Write Latencies in Multiprocessors with Two Level CacheJulio Sahuquillo, Ana Pont. 10333-10336 [doi]
• Efficient High-Speed CMOS Design by Layout Based Schematic MethodFenghao Mu, Christer Svensson. 10337-10340 [doi]
• A Miniature Serial-Data SIMD ArchitecturePer Larsson-Edefors. 10341-10344 [doi]
• Cache Probabilistic Modeling for Basic Sparse Algebra Kernels Involving Matrices with a Non Uniform DistributionRamon Doallo, Basilio B. Fraguela, Emilio L. Zapata. 10345 [doi]
• Estimation and Consideration of Interconnection Delays during High-Level SynthesisJonas Hallberg, Zebo Peng. 10349-10356 [doi]
• Design of Control Dominated Hardware Based on Formal MethodsWerner Grass, Stefan Lenk, Christine Sontheim. 10357-10364 [doi]
• A Method for Mapping DSP Algorithms into Application Specific StructuresAnatoli Sergyienko, Juri Kanevski, Oleg Maslennikov, Roman Wyrzykowski. 10365 [doi]
• Simulation of a Component-Oriented Voter Library for Dependable Control ApplicationsG. Latif-Shabgahi, Julian M. Bass, Stuart Bennett. 10372-10378 [doi]
• The EFTOS Voting Farm: A Software Tool for Fault Masking in Message Passing Parallel EnvironmentsVincenzo De Florio, Geert Deconinck, Rudy Lauwereins. 10379-10386 [doi]
• Generating Multiple Diverse Software Versions with Genetic ProgrammingRobert Feldt. 10387 [doi]
• An Experimental Study about Diskless CheckpointingLuís Moura Silva, João Gabriel Silva. 10395-10402 [doi]
• Distributed Checkpoint Algorithms to Avoid Roll-Back PropagationFranco Zambonelli. 10403-10410 [doi]
• Dynamic Acceptance Tests for Complex ControllersR. Stroph, T. Clarke. 10411 [doi]
• Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer SystemDaniel Gil, Juan Carlos Baraza, J. V. Busquets, Pedro J. Gil. 10418-10425 [doi]
• On-the-Fly Model Checking of Program Runs for Automated DebuggingMaximilian Frey, Bernd-Holger Schlingloff. 10426 [doi]
• On the Effectiveness of Slicing Hierarchical State Machines: A Case StudyMats Per Erik Heimdahl, Jeffrey M. Thompson, Michael W. Whalen. 10435-10444 [doi]
• Engineering Safe, Real-Time Distributed Control SystemsPeter R. Croll, Chris Rudram, Colin Chambers, Naoshi Uchihira. 10445-10452 [doi]
• Towards Standard-Based Specification and Design of Embedded Real-Time SystemsRoman Gumzej, Matjaz Colnaric, Domen Verber, Wolfgang A. Halang. 10453 [doi]
• A 32-Bit Risc Processor with Concurrent Error DetectionA. Maamar, G. Russell. 10461-10467 [doi]
• An Experimental Investigation of Message Latencies in the Totem Protocol in the Presence of FaultsHolger Karl, Matthias Werner, Lars Küttner. 10468-10475 [doi]
• Approaches for Scheduling of Triggered Transactions in Real-Time Active Database SystemsKam-yiu Lam, Tony S. H. Lee. 10476 [doi]
• Multi-View Specification of CSCW ApplicationsMarjeta Frey-Pucko, Maximilian Frey. 20484-20491 [doi]
• Modeling and Querying Video DatabasesCyril Decleir, Mohand-Said Hacid, Jacques Kouloumdjian. 20492 [doi]
• Modeling Client/Server Interactions by Means of Dynamic SystemsF. Calzolari, Paolo Tonella. 20499-20505 [doi]
• A Master-Medium-Based Interactive Synchronization Control Scheme for Distributed Multimedia SystemsChung-Ming Huang, Chian Wang, Cheng-Yi Kuo. 20506-20513 [doi]
• Improved Multimedia Server I/O SubsystemsMichael Weeks, Hadj Batatia, Reza Sotudeh. 20514 [doi]
• Address Resolution Model and Traffic Control for Multimedia Data Transmission with QoS Guarantees between ATM and EthernetYu-Chang Chen, Chein-Chih Chang, Wen-Shyong Hsieh, Chu-Sing Yang. 20520-20527 [doi]
• Real-Time Disparity Information Compression in 3D Teleconferencing SystemsD. Papadimatos, Theodore Antonakopoulos, Vassilios Makios. 20528-20535 [doi]
• Comparison between Optical SCM Systems for Multimedia ApplicationsSilvello Betti, E. Bravi, M. Giaconi. 20536-20543 [doi]
• Dealing with One-Timer-Documents in Web CachingAdam Belloum, Louis O. Hertzberger. 20544 [doi]
• Efficient Memory Management in VOD Disk Array Servers Using Per-Storage-Device BufferingAlberto García-Martínez, Jesús Fernández-Conde, Ángel Viña. 20551-20558 [doi]
• The Sum-Absolute-Difference Motion Estimation AcceleratoStamatis Vassiliadis, Edwin A. Hakkennes, J. S. S. M. Wong, Gerald G. Pechanek. 20559-20566 [doi]
• Dimensioning of a Multimedia Switching BusKimmo Kaario, Pertti Raatikainen. 20567 [doi]
• Retransmission Scheme for MPEG Streams in Mission Critical Multimedia ApplicationsSugh-Hoon Lee, Sungyoung Lee. 20574-20580 [doi]
• PROMIS: A Reliable Real-Time Network Management Tool for Wide Area NetworksEduardo Magaña, Javier Aracil, Jesús E. Villadangos. 20581-20588 [doi]
• Design and Performance Evaluation of a Buffer Replacement Algorithm Utilizing Reference Interval InformationJeong-Gook Koh, Gil Yong Kim. 20589-20596 [doi]
• Broadband Services in the Access Network: A Technical-Economic Comparison of Wired and Wireless SystemsGaetano Vespasiano, Maria Stella Iacobucci, Pasquale Palma. 20597 [doi]
• Designing Interactive Multimedia Learning Systems on the Web Using a New Graphical Navigational Design TechniqueEng Huat Ng, Stu Wade. 20604-20609 [doi]
• Experiments with MHEG Player/Studio: An Interactive Hypermedia Visualization and Authoring SystemSeungtaek Oh, Yung Yi, Seunghoon Jeong, Yanghee Choi, Younghwa Ko. 20610-20615 [doi]
• Integration of Image Processing and Automated Testing in a Manufacturing Client-Server NetworkPerfecto Mariño, Miguel Angel Domínguez. 20616 [doi]
• Using Sound to Communicate Program ExecutionDimitrios I. Rigas, James L. Alty. 20625-20632 [doi]
• Image Compression Using the Wavelet Transform on Textural Regions of InterestDimitris A. Karras, S. A. Karkanis, Basil G. Mertzios. 20633-20639 [doi]
• A Methodology for Design of Large Hypermedia SystemsBob Newman. 20640 [doi]
• Novel Internal Units for a Neural Network Based Adaptive Fuzzy Inference SystemsNigel Steele, A. Dobnikar. 20647 [doi]
• A Transparent and Flexible Development Environment for Rapid Design of Cognitive SystemsAndreas König, Michael Eberhardt, Robert Wenzel. 20655-20662 [doi]
• On Function Approximators Implementable as Layered Neural NetworksIon Ciuca. 20663-20669 [doi]
• On Feature Selection Methods in the Application of Neural Networks to Social SciencesDimitris A. Karras, I. J. Marmatsouri, E. J. Hatzakis, N. Paritsis. 20670 [doi]
• Implementation of a RBF Network Based on Possibilistic ReasoningPeter Glösekötter, Andreas Kanstein, Stefan Jung, Karl Goser. 20677-20682 [doi]
• A Novel Neural Network Training Technique Based on a Multi-Algorithm Constrained Optimization StrategyDimitris A. Karras, Isaac E. Lagaris. 20683-20687 [doi]
• FPGA Based Implementation of a Hopfield Neural Network for Solving Constraint Satisfaction ProblemsDavid Abramson, Kate A. Smith, Paul Logothetis, David Duke. 20688-20693 [doi]
• Hybrid Number Representation for the FPGA-Realization of a Versatile Neuro-ProcessorHarald Wüst, Klaus Kasper, Herbert Reininger. 20694 [doi]
• Genetic Algorithm with Multistart Search for the p-Hub Median ProblemMelquíades Pérez Pérez, Francisco Almeida, J. Marcos Moreno-Vega. 20702-20707 [doi]
• A Genetic Algorithm for Scheduling Tasks in a Real-Time Distributed SystemYannick Monnier, Jean-Pierre Beauvais, Anne-Marie Déplanche. 20708-20714 [doi]
• Solving the Satisfiability Problem by a Parallel Celluar Genetic AlgorithmGianluigi Folino, Clara Pizzuti, Giandomenico Spezzano. 20715 [doi]
• Where is Knowledge in Computational Intelligence?: On the Reduction of the Knowledge Level to the Level BelowJosé Mira, Juan Carlos Herrero, Ana E. Delgado García. 20723-20732 [doi]
• A Fast Metric Approach to Feature Subset SelectionTony Y. T. Chan. 20733-20736 [doi]
• An Abductive Method for Solving a Treatment ProblemSamuel Túnez, Roque Marín, Isabel María del Águila, Alfonso Bosch, Manuel Torres. 20737-20744 [doi]
• Improving the Performance of Fuzzy Systems by Using Local PartitioningJouni Raitamäki. 20745 [doi]
• A Structured Approach to Software Process ModellingXavier Franch, Josep M. Ribó Balust. 20753-20762 [doi]
• Towards Continuous Process Development: Designing SQA Function for Large Organisation NeedsTapani Kilpi. 20763-20768 [doi]
• Process-Product Unification in a Decentralized Environment: A Status ReportAkif Günes Koru, Elif Demirörs, Onur Demirörs. 20769-20774 [doi]
• Process Improvement by Change of Paradigm in an Agriculture CompanyR. Maier. 20775 [doi]
• Managing Change in Software Development Using a Process Improvement ApproachW. Lam, V. Shankararaman. 20779-20786 [doi]
• CMOS - Change Management Of Software ESSI PIE nr. 23661Emilio Benedetti, Luisa Consolini. 20787-20793 [doi]
• A Change Process Model in an SCM ToolIvica Crnkovic. 20794 [doi]
• Measuring the Effectiveness of Introducing New Methods in the Software Development ProcessMichael Winokur, Arie Grinman, Israel Yosha, Reuven Gallant. 20800-20807 [doi]
• Software Process Improvement Planning with Neural NetworksVolkmar H. Haase. 20808-20815 [doi]
• An Approach to Schedule Estimation and Tracking for Rapid Development ProjectsIgnac Lovrek, Vjekoslav Sinkovic, Dejan Grahovac, Antun Caric. 20816-20823 [doi]
• Performance and Quality Aspects of Virtual Software EnterprisesKlaus D. Zesar, Michael Zechner, Peter Salhofer, Gerhard Schuster, Gerfried Muelleitner. 20824 [doi]
• Test Tools for the Year 2000 ChallengesHareton K. N. Leung. 20830-20837 [doi]
• Pragmatic Method for Interoperability Test Suite DerivationMazen Malek, Sarolta Dibuz. 20838-20844 [doi]
• Test Selection Based on Implementation SpecificationV. V. Ostapenko. 20845 [doi]
• Software Quality Assurance - Concepts and MisconceptionsPer Runeson, Peter Isacsson. 20853-20859 [doi]
• Does ISO 9001 Increase Software Development Maturity?Anne Mette Jonassen Hass, Jørn Johansen, Jan Pries-Heje. 20860-20866 [doi]
• Practical Aspects on the Assessment of a Review ProcessJanne Kiiskilä. 20867-20870 [doi]
• Software Development Process Improvements by Metrics - A Taming of ChaosHans Erik Stokke. 20871 [doi]
• A Survey of European Reuse Experiences: Initial ResultsMichel Ezran, Maurizio Morisio, Colin Tully. 20875-20881 [doi]
• A Multi-Tiered Classification Scheme for Component RetrievalEwan Smith, Adil Al-Yasiri, Madjid Merabti. 20882-20889 [doi]
• A Reuse-Based Software Process Based on Domain Analysis and OO FrameworkElisabetta Morandin, Gianfranco Stellucci, Francesco Baruchelli. 20890 [doi]
• A Product-Process Dependency Definition MethodDirk Hamann, Janne Järvinen, Andreas Birk, Dietmar Pfahl. 20898-20904 [doi]
• Product-Based Software Process Improvement for Embedded SystemsJorma Taramaa, Munish Khurana, Pasi Kuvaja, Jari Lehtonen, Markku Oivo, Veikko Seppänen. 20905-20912 [doi]
• The Improvement of a Software Design Methodology by Encapsulating Knowledge from CodeBarry McCollum, Vaughan Purnell, Patrick H. Corr, Peter Milligan. 20913-20918 [doi]
• Improvement of Control Software for Automatic Logistic Systems Using Executable Environment ModelsChristian Kreiner, Christian Steger, Reinhold Weiss. 20919-20923 [doi]
• From Design to Implementation Using the Parallel Program GeneratorJosé R. P. Ribeiro, Nilton C. da Silva, Roxana G. Morón, Célio Estevan Morón. 20924 [doi]
• The World Wide Wait: Where Does the Time Go?Colin Allison, Martin Bramley, Jose Serrano. 20932-20938 [doi]
• Two-Level Communication Protocol for a Web Operating System (WOS?)Gilbert Babin, Peter G. Kropf, Herwig Unger. 20939-20944 [doi]
• Wide-Area High-Performance Computing Using WorkstationsDjamshid Tavangarian, Peter Eschholz, Michael Koch, Stephan Preuß. 20945 [doi]
• SMP PCs: A Case Study on Cluster ComputingAntônio Augusto Fröhlich, Wolfgang Schröder-Preikschat. 20953-20960 [doi]
• Bulk Synchronous Parallel without BarriersJosé L. Roda, Casiano Rodríguez, Daniel González-Morales, Francisco Almeida. 20961-20968 [doi]
• Scalability of Multicast Based Synchronization MethodsBettina Schnor, Stefan Petri, Matthias Becker. 20969-20975 [doi]
• User-Profile Adaptable Resource Management System for Workstation Cluster ArchitecturesMahmoud Mofaddel, Djamshid Tavangarian. 20976 [doi]
• The Pros and Cons of Web ProgrammingFerenc Vajda. 20984-20988 [doi]
• Experiences with the Use of CORBAEila Niemelä, Mikko Holappa. 20989-20996 [doi]
• Composite Objects: Real-Time Programming with CORBAAndreas Polze, Lui Sha. 20997 [doi]
• Load Management with Mobile AgentsWolfgang Obelöer, Claus Grewe, Holger Pals. 21005-21012 [doi]
• A Real-Time IPC Service over ATM Networks for the Chorus Distributed SystemChristophe Lizzi, Eric Gressier-Soudan. 21013-21020 [doi]
• Object Organization on a Single Broadcast Channel in a Global Information Sharing EnvironmentAli R. Hurson, Y. C. Chehadeh, Les L. Miller. 21021 [doi]
• DRoPS: Kernel Support For Runtime Adaptable ProtocolsR. S. Fish, J. M. Graham, Roger J. Loader. 21029-21036 [doi]
• Managing Processes with Network Objects and Their TranslationDmitry Arapov, Victor Ivannikov, Alexey Kalinov, Alexey L. Lastovetsky, Ilya Ledovskih. 21037 [doi]
• Parallelization of Volume Visualization on Computer NetworksMoritz Schulé, Michael Meißner. 21045-21052 [doi]
• Regional Weather Prediction on Small Network of WorkstationsAdrianos Lachanas, Paraskevas Evripidou, Silas Michaelides. 21053-21060 [doi]
• A System for Cooperative Work in the Medical DomainEdelhard Becker, Roland Hoyss, Thomas Grunert. 21061 [doi]
• Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World ProblemManfred Glesner, Matthias Rychetsky, Stefan Ortmann. 21068 [doi]