Table of Contents

• A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional MemoryOriol Arcas, Philipp Kirchhofer, Nehir Sönmez, Martin Schindewolf, Osman S. Unsal, Wolfgang Karl, Adrián Cristal. 1-8 [doi]
• Towards a Universal FPGA Matrix-Vector Multiplication ArchitectureSrinidhi Kestur, John D. Davis, Eric S. Chung. 9-16 [doi]
• Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator SystemsJongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski. 17-24 [doi]
• Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point MultipliersManish Kumar Jaiswal, Ray C. C. Cheung. 25-28 [doi]
• Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGAEduardo Gudis, Gooitzen van der Wal, Sujit Kuthirummal, Sek Chai. 29-32 [doi]
• A Mixed Precision Methodology for Mathematical OptimisationGary C. T. Chow, Wayne Luk, Philip Heng Wai Leong. 33-36 [doi]
• Go Ahead: A Partial Reconfiguration FrameworkChristian Beckhoff, Dirk Koch, Jim Torresen. 37-44 [doi]
• On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module LibraryChristopher Dennl, Daniel Ziener, Jürgen Teich. 45-52 [doi]
• Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific ComputingJuan Luis Jerez, George A. Constantinides, Eric C. Kerrigan. 53-60 [doi]
• Formic: Cost-efficient and Scalable Prototyping of Manycore ArchitecturesSpyros Lyberis, George Kalokerinos, Michalis Lygerakis, Vassilis Papaefstathiou, Dimitrios Tsaliagkos, Manolis Katevenis, Dionisios N. Pnevmatikatos, Dimitris S. Nikolopoulos. 61-64 [doi]
• Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based AcceleratorsKumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda. 65-68 [doi]
• FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIPXiaolin Chen, Andreas Minwegen, Yahia Hassan, David Kammler, Shuai Li, Torsten Kempf, Anupam Chattopadhyay, Gerd Ascheid. 69-76 [doi]
• FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++Hélène Martorell, Nachiket Kapre. 77-84 [doi]
• FPGA-based Acceleration for Tracking Audio Effects in MoviesMihalis Psarakis, Aggelos Pikrakis, Giannis Dendrinos. 85-92 [doi]
• ZUMA: An Open FPGA Overlay ArchitectureAlexander Brant, Guy G. F. Lemieux. 93-96 [doi]
• Efficient Query Processing for Web Search Engine with FPGAsJing Yan, Zhanxiang Zhao, Ning-Yi Xu, Xi Jin, Lin-Tao Zhang, Feng-hsiung Hsu. 97-100 [doi]
• Power Management Strategies for Serial RapidIO Endpoints in FPGAsMoritz Schmid, Frank Hannig, Jürgen Teich. 101-108 [doi]
• Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency ScalingJoshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung. 109-116 [doi]
• An Extensible and Portable Tool Suite for Managing Multi-Node FPGA SystemsYamuna Rajasekhar, Rahul R. Sharma, Ron Sass. 117-120 [doi]
• Remote Execution in Distributed Memory MPSoCRémi Busseuil, Luciano Ost, Rafael Garibotti, Gilles Sassatelli, Michel Robert. 121-124 [doi]
• A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAsIsaac Liu, Edward A. Lee, Matthew Viele, Guoqiang Wang, Hugo A. Andrade. 125-132 [doi]
• Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network SimulationSimon W. Moore, Paul J. Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar. 133-140 [doi]
• Emulating Mammalian Vision on Reconfigurable HardwareSrinidhi Kestur, Mi Sun Park, Jagdish Sabarad, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla. 141-148 [doi]
• Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAsGabriel L. Nazar, Luigi Carro. 149-152 [doi]
• A Custom Precision Based Architecture for Accelerating Parallel Tempering MCMC on FPGAs without Introducing Sampling ErrorGrigorios Mingas, Christos-Savvas Bouganis. 153-156 [doi]
• Exploiting Memory-Level Parallelism in Reconfigurable AcceleratorsShaoyi Cheng, Mingjie Lin, Hao Jun Liu, Simon Scott, John Wawrzynek. 157-160 [doi]
• Hardware Acceleration of Short Read MappingCorey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo. 161-168 [doi]
• Short-Read Mapping by a Systolic Custom FPGA ComputationThomas B. Preußer, Oliver Knodel, Rainer G. Spallek. 169-176 [doi]
• FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment through Pipelined PrefilteringAtabak Mahram, Martin C. Herbordt. 177-183 [doi]
• Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA AcceleratorWen Tang, Wendi Wang, Bo Duan, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun. 184-187 [doi]
• Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem SizesBerkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe. 188-191 [doi]
• Specifying Compiler Strategies for FPGA-based SystemsJoão M. P. Cardoso, João Teixeira, José C. Alves, Ricardo Nobre, Pedro C. Diniz, José Gabriel F. Coutinho, Wayne Luk. 192-199 [doi]
• Bus-based MPSoC Security through Communication Protection: A Latency-efficient AlternativePascal Cotret, Jérémie Crenne, Guy Gogniat, Jean-Philippe Diguet. 200-207 [doi]
• PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable ProcessorsLars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jörg Henkel. 208-215 [doi]
• RIFFA: A Reusable Integration Framework for FPGA AcceleratorsMatthew Jacobsen, Yoav Freund, Ryan Kastner. 216-219 [doi]
• Groundhog - A Serial ATA Host Bus Adapter (HBA) for FPGAsLouis Woods, Ken Eguro. 220-223 [doi]
• Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder CaseG. Falcao, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne. 224-231 [doi]
• Accelerating a Random Forest Classifier: Multi-Core, GP-GPU, or FPGA?Brian Van Essen, Chris Macaraeg, Maya Gokhale, Ryan Prenger. 232-239 [doi]
• Cognitive Radio Universal Software HardwareGeorge Eichinger, Kaushik Chowdhury, Miriam Leeser. 240 [doi]
• Designing Flexible Reconfigurable Regions to Relocate Partial BitstreamsYoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 241 [doi]
• EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient MannerAndreas Ehliar. 242 [doi]
• Implementing Murf: Accelerating Large State Space Exploration on FPGAsMary Ellen Tie, Miriam Leeser. 243 [doi]
• ScalaPipe: A Streaming Application GeneratorJoseph G. Wingbermuehle, Roger D. Chamberlain, Ron K. Cytron. 244 [doi]
• VENICE: A Compact Vector Processor for FPGA ApplicationsAaron Severance, Guy Lemieux. 245 [doi]