Table of Contents

• Technology Scaling in FPGAs: Trends in Applications and ArchitecturesLesley Shannon, Veronica Cojocaru, Cong Nguyen Dao, Philip H. W. Leong. 1-8 [doi]
• Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAsAaron Landy, Greg Stitt. 9-16 [doi]
• Rapid Overlay Builder for Xilinx FPGAsMichael Xi Yue, Dirk Koch, Guy G. F. Lemieux. 17-20 [doi]
• Adjustable-Cost Overlays for Runtime CompilationJames Coole, Greg Stitt. 21-24 [doi]
• Efficient Overlay Architecture Based on DSP BlocksAbhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell. 25-28 [doi]
• High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow ModelMohamed W. Hassan, Ahmed E. Helal, Yasser Y. Hanafy. 29 [doi]
• Cycle-Accurate Replay and Debugging of Running FPGA SystemsSunil Shukla, David F. Bacon. 30 [doi]
• Heterogeneous Platform to Accelerate Compute Intensive ApplicationsSanthosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal. 31 [doi]
• High Performance Memory Accesses on FPGA-SoCs: A Quantitative AnalysisMatthias Gobel, Chi Ching Chi, Mauricio Alvarez Mesa, Ben H. H. Juurlink. 32 [doi]
• Sparse Graph Processing with Soft-ProcessorsNachiket Kapre. 33 [doi]
• Improving Data Partitioning Performance on OpenCL-Based FPGAsZe-ke Wang, Bingsheng He, Wei Zhang. 34 [doi]
• Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTsHongyuan Ding, Miaoqing Huang. 35 [doi]
• Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable HardwareDavid Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley. 36-43 [doi]
• Enabling High Throughput and Virtualization for Traffic Classification on FPGAYun R. Qu, Viktor K. Prasanna. 44-51 [doi]
• A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAsJeremy Fowers, Joo-Young Kim, Doug Burger, Scott Hauck. 52-59 [doi]
• Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGAThiem Van Chu, Shimpei Sato, Kenji Kise. 60-63 [doi]
• Accelerating SpMV on FPGAs by Compressing Nonzero ValuesPaul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk. 64-67 [doi]
• Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC ClusterPradeep Moorthy, Nachiket Kapre. 68-75 [doi]
• Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector ProcessorsGopalakrishna Hegde, Nachiket Kapre. 76-83 [doi]
• Autotuning FPGA Design Parameters for Performance and PowerAzamat Mametjanov, Prasanna Balaprakash, Chekuri Choudary, Paul D. Hovland, Stefan M. Wild, Gerald Sabin. 84-91 [doi]
• FIR Filter Based on Stochastic Computing with Reconfigurable Digital FabricMohammed Alawad, Mingjie Lin. 92-95 [doi]
• Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case StudyMohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján. 96 [doi]
• Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC DecodersJoão Andrade, Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes. 97 [doi]
• Design of a Distributed Compressor for Astronomy SSDBo Peng, Xi Jin, Tianqi Wang, Xueliang Du. 98 [doi]
• Scalable Key/Value Search in DatacentersJohn W. Lockwood. 99 [doi]
• Function Proxies for Improved Resource Sharing in High Level SynthesisMarco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi. 100 [doi]
• Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAsCheng Liu, Hayden Kwok-Hay So. 101 [doi]
• Adaptive Configurable Transactional Memory for Multi-processor FPGA PlatformsJeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono. 102 [doi]
• Pipelined Genetic PropagationLiucheng Guo, Ce Guo, David B. Thomas, Wayne Luk. 103-110 [doi]
• FPGA Acceleration of Recurrent Neural Network Based Language ModelSicheng Li, Chunpeng Wu, Hai Li, Boxun Li, Yu Wang, Qinru Qiu. 111-118 [doi]
• Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud ComputingNachiket Kapre, Bibin Chandrashekaran, Harnhua Ng, Kirvy Teo. 119-126 [doi]
• Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAsJeffrey B. Goeders, Steven J. E. Wilton. 127-134 [doi]
• High-Level Debugging and Verification for FPGA-Based Multicore ArchitecturesOriol Arcas-Abella, Adrián Cristal, Osman S. Unsal. 135-142 [doi]
• Estimating Soft Processor Soft Error Sensitivity through Fault InjectionNathan A. Harward, Michael R. Gardiner, Luke W. Hsiao, Michael J. Wirthlin. 143-150 [doi]
• Protecting against Cryptographic Trojans in FPGAsPawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux, Russell Tessier. 151-154 [doi]
• Automatic High-Level Hardware Checkpoint Selection for Reconfigurable SystemsAlban Bourge, Olivier Muller, Frédéric Rousseau. 155-158 [doi]
• Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLSJunyi Liu, Samuel Bayliss, George A. Constantinides. 159-162 [doi]
• HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGABehzad Salami, Oriol Arcas-Abella, Nehir Sönmez. 163 [doi]
• Accelerating Big Data Analytics Using FPGAsKatayoun Neshatpour, Maria Malik, Mohammad Ali Ghodrat, Houman Homayoun. 164 [doi]
• Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing SystemVenkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser. 165 [doi]
• A System on Reconfigurable Chip for Handwritten Digit RecognitionLuca Bochi Saldanha, Christophe Bobda. 166 [doi]
• An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCLYuliang Pu, Jun Peng, Letian Huang, John Chen. 167-170 [doi]
• Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic BehaviourFrancis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, T. N. Palmer. 171-178 [doi]
• Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude CoordinatesRoger Moussalli, Mudhakar Srivatsa, Sameh W. Asaad. 179-186 [doi]
• SSketch: An Automated Framework for Streaming Sketch-Based Analysis of Big Data on FPGABita Darvish Rouhani, Ebrahim M. Songhori, Azalia Mirhoseini, Farinaz Koushanfar. 187-194 [doi]
• An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool ArchitecturesJens Korinth, David de la Chevallerie, Andreas Koch. 195-198 [doi]
• A Novel High-Throughput Acceleration Engine for Read AlignmentYu-Ting Chen, Jason Cong, Jie Lei, Peng Wei. 199-202 [doi]
• A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data StoragesDongyang Li, Qing Yang, Qingbo Wang, Cyril Guyot, Ashwin Narasimha, Dejan Vucinic, Zvonimir Bandic. 203-206 [doi]
• Modular SRAM-Based Binary Content-Addressable MemoriesAmeer M. S. Abdelhadi, Guy G. F. Lemieux. 207-214 [doi]
• A Low-Latency, Low-Area Hardware Oblivious RAM ControllerChristopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios Serpanos, Srinivas Devadas. 215-222 [doi]
• Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout AreaFarheen Fatima Khan, Andy Ye. 223-226 [doi]
• Offset Pipelined Scheduling: Conditional Branching for CGRAsAaron Wood, Scott Hauck. 227-230 [doi]
• A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data ProcessingXabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin Hand, Robert Carlson, Emre Ozer. 231 [doi]
• FPGA Design for PCANet Deep Learning NetworkYuteng Zhou, Wei Wang, Xinming Huang. 232 [doi]
• Functional Locking Modules for Design Protection of Intellectual Property CoresBrice Colombier, Lilian Bossuet. 233 [doi]
• Virtual Channel and Switch Allocation for Low Latency Network-on-Chip RoutersAlireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono. 234 [doi]
• Early Experiences with OpenCL on FPGAs: Convolution Case StudyCarlos Rodriguez-Donate, Guillermo Botella, C. Garcia, Eduardo Cabal-Yepez, Manuel Prieto-Matías. 235 [doi]
• Optimizing Residue Number Reverse Converters through Bitwise Arithmetic on FPGAsBangtian Liu, Haohuan Fu, Lin Gan, Wenlai Zhao, Guangwen Yang. 236-243 [doi]
• A Reconfigurable Multiclass Support Vector Machine Architecture for Real-Time Embedded Systems ClassificationJason Kane, Robert Hernandez, Qing Yang. 244-251 [doi]
• Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements DetectionMarco Rabozzi, Antonio Miele, Marco D. Santambrogio. 252-255 [doi]
• Designing Partial Bitstreams for Multiple Xilinx FPGA PartitionsVictor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra. 256-259 [doi]