Table of Contents

• High Level System desing using HiLes DesignerJ.-C. Hammon, Daniel Esteve, Pascal Pampagnin. 1-12 [doi]
• VHDL-AMS code gneration from UML structural representationsC. T. Carr, T. Martin McGinnity, L. J. McDaid. 12-25
• Evalution/Testing of Compact Device Model ImplementationLaurent Lemaitre. 25-30 [doi]
• A language to desing generators of analog functions (poster)Marie-Minerve Louërat, Tuong P. Nguyen, Vincent Bourguet, L. de Lamarre, Alain Greiner. 30-32 [doi]
• SystemC Simulation of Continuous-Time Sigma-Delta Analog-Digital Converters in the Presence of Non-linearitiesHui Zhang, Alex Doboli. 32-44
• HEAVEN: A Framework for the Refinement of Heterogeneous SystemsRüdiger Schroll, Christoph Grimm, Klaus Waldschmidt. 44-56 [doi]
• Semi-Symbolic Modeling and Analysis of Noise in Heterogeneous Systems Christoph Grimm, Wilhelm Heupke, Klaus Waldschmidt. 56-68 [doi]
• High Level Self-adjusted Models and VHDL-AMS; Application for a freguency synthesizer modellingS. Loued, Ahmed Fakhfakh, Mourad Loulou, Nouri Masmoudi, Yannick Hervé. 68-76 [doi]
• A novel approach to mixed-domain behavioral modeling of ferromagnetic hysteresis in VHDL-AMSPeter R. Wilson, Tom J. Kazmierski. 76-80 [doi]
• Modeling of the ultrasonic nonlinear propagation with VHDL-AMSRachid Guelaz, Djilali Kourtiche, Yannick Hervé, Mustapha Nadi. 80-91 [doi]
• Requirements and Verifications through an extension of VHDL-AMSYannick Hervé, Ahmed Fakhfakh. 91-100 [doi]
• Mixed Nets, Conversion Models, and VHDL-AMSJ. Shields, Ernst Christen. 100-112 [doi]
• Monte Carlo Simulation Using VHDL-AMSE.-P. Wagner, J. Haase. 112-123 [doi]
• Optical Network On-chip Multi-Domain modeling using SystemCEmmanuel Drouard, Matthieu Briere, Fabien Mieyeville, Ian O Connor, X. Letartre. 123-135 [doi]
• Early Prediction of Conducted-Mode Emission of complex IC sAnne-Marie Trullemans-Anckaert, Richard Perdriau, Mohammed Ramdani, Jean-Luc Levant. 135-144 [doi]
• A VHDL-AMS Configuration for Active Pixel SensorsF. Dadouche, A. Alexandre, Bertrand Granado, Andréa Pinna, Patrick Garda. 144-156 [doi]
• Behavioural modelling of a power amplifier in VHDL-AMSM. Garon, Jean-Francois Diouris, Serge Toutain, Emmanuel Cottais, Yide Wang. 156-158 [doi]
• Practical Case Example of Inertial MEMS Modeling with VHDL-AMSE. Martin, C. Ferrer. 158-168 [doi]
• SoC modelling for virtual prototyping with VHDL-AMSPatricia Desgreys, Yannick Hervé, Jean Oudinot, S. Snaidero, Mohamed Karray. 168-180 [doi]
• Model Based Testing and Refinement in MDA Based DevelopentIan Oliver. 180-192 [doi]
• Application Driven Methodology for Development of Communicating SystemsSari Leppänen, Markku Turunen, Ian Oliver. 192-204 [doi]
• A Model-driven Approach to Configuration of TTA-based Protocol Processing PlatformsDragos Truscan. 204-216 [doi]
• Mapping UML Descriptions to the Raven Input LanguageIan Oliver. 216-228 [doi]
• Error Estimation in Model-Driven Development for Real-Time SoftwareOana Florescu, Jeroen Voeten, Jinfeng Huang, Henk Corporaal. 228-240 [doi]
• Metamodels and MDA Transformations for Embedded SystemsLossan Bonde, Cédric Dumoulin, Jean-Luc Dekeyser. 240-252 [doi]
• Timing Performances of Automatically Generated Code Using MDA ApproachesMathieu Maranzana, J.-F. Ponsignon, Jean-Louis Sourrouille, F. Bernier. 252-12 [doi]
• Predictability in Real-time System Development (1) Semantics Support from Development Languages Jinfeng Huang, Jeroen Voeten, Andre Ventevogel. 264-278 [doi]
• Predictability in Real-time System Development (2) A Case Study Jinfeng Huang, Jeroen Voeten, Piet van der Putten, Andre Ventevogel. 278-289 [doi]
• Regular Hardware Architecture Modeling with UML2Arnaud Cuccuru, Pierre Boulet, Jean-Luc Dekeyser. 289-301 [doi]
• UML System-Level Analysis and Design of Secure Communication Schemes for Embedded SystemsMauro Prevostini, Giuseppe Piscopo, I. Stefanini. 301-313 [doi]
• UML Specifications Towards a Codesign EnvironmentMauro Prevostini, M. Lajolo, A. S. Basu. 313-325 [doi]
• UML-Executable Functional Models of electronic systems in the VIPERS Virtual Prototyping MethodologyPaul F. Lister, Vincenzo Trignano, Milke C. Bassett. 325-337 [doi]
• Fast Bit-Accurate C++ Datatypes For Functional System Verification and SynthesisAndrés Takach, S. Waters, P. Gutberlet. 337-345 [doi]
• A Generic Simulation Framework for Multiprocessor ArchitecturesMario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher. 345-355 [doi]
• A Heterogeneous Co-simulation Environment for Complex Embedded Telecommunication SystemsFotios Gioulekas, Michael K. Birbas, Nikos S. Voros, George Kouklaras, Alexios N. Birbas. 355-366 [doi]
• An Abstract Communication Bus Model for Performance Estimation in SoCs with SystemC (short paper)Rocco Le Moigne, Olivier Pasquier, Jean Paul Calvez. 366-378 [doi]
• An automatic communication synthesis for high level SOC desing using transaction level modelling (poster)E. Turbatu, Samy Meftali, Smaïl Niar, Jean-Luc Dekeyser. 378-380 [doi]
• Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded SystemsP. Hastono, Stephan Klaus, Sorin A. Huss. 380-392 [doi]
• On Actors and Objects - OOP in System Level DesignJoachim K. Anlauf, Philipp A. Hartmann. 392-404 [doi]
• Heterogeneous System-Level Specification in SystemCFernando Herrera, Pablo Sánchez, Eugenio Villar. 404-416 [doi]
• Performance Analysis and Automated C++ Modularization Using Module-Adapters for SystemCNico Bannow, Karsten Haug, Wolfgang Rosenstiel. 416-428 [doi]
• SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-ChipKari Tiensyrjä, Miroslav Cupák, Kostas Masselos, Marko Pettissalo. 428-440 [doi]
• Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSSAndreas Schallenberg, Frank Oppenheimer, Wolfgang Nebel. 440-452 [doi]
• MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing ApplicationsM. Samyn, Samy Meftali, Jean-Luc Dekeyser. 452-463 [doi]
• Designing NOCs with a parallel extension of cM. Forsell. 463-475 [doi]
• Experimenting Object-Oriented System-Level Design in the ATM domainLuigi Pomante. 475-484 [doi]
• SystemC Based Design Space Exploration for Power Aware Smart CardsUlrich Neffe, Christian Steger, Reinhold Weiss, Andreas Mühlberger, Edgar Rieger, Klaus Rothbart. 484-493 [doi]
• Improving IP core reuse through the application of the meta-language xHDLMarcos M. A. Sanchez, Fernandez Herrero, Vallejo M. Lopez. 493-505 [doi]
• SystemVerilog: Interface Based DesignP. Jensen, Wolfgang Ecker, T. Kruse, Martin Zambaldi. 505-518 [doi]
• Transaction Level Modeling in JavaSherif G. Aly, Ashraf M. Salem. 518-526 [doi]
• An Intermediate Level HDL for System Level DesignJean-Pierre David, Etienne Bergeron. 526-536 [doi]
• Extending the RASSP model for VerificationMartin Zambaldi, Wolfgang Ecker. 536-544 [doi]
• A Methodology for Embedded System Design supporting Layered PlatformsStefan Förster, André Windisch, M. Fischer, Dieter Monjau, Wolfram Hardt. 544-556 [doi]
• A Formal Verification Approach for IP-based DesignsDaniel Karlsson, Petru Eles, Zebo Peng. 556-568 [doi]
• The Formal Simulation Semantics of SystemVerilogMartin Zambaldi, Wolfgang Ecker, T. Kruse, W. Müller. 568-578 [doi]
• Temporal validation of Real Time multitasking applications based on communicating timed automataMostefa Belarbi, Jean-Philippe Babau, Jean-Jacques Schwarz. 578-586 [doi]
• A Functional Programming Framework of Heterogeneous Model of Computation for System DesignDeepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla. 586-598 [doi]
• A hardware/software codesign framework for developing complex embedded systems using formal model refinementNikos S. Voros, Colin F. Snook, Stefan Hallerstede, Thierry Lecomte. 598-612 [doi]
• Derivation of SystemC code from abstract system modelsDominique Cansell, J.-F. Culat, Dominique Méry, Cyril Proch. 612-624 [doi]
• Circuit Design by Refinement in EventB1Stefan Hallerstede, Y. Zimmermann. 624-637 [doi]
• Reuse of SML module system for the B languageDorian Petit, Vincent Poirriez, Georges Mariano. 637-649 [doi]
• Enabling SystemC Verification using Abstract State MachinesAmjad Gawanmeh, Ali Habibi, Sofiène Tahar. 649-661 [doi]
• GBLD: A Formal Model for Layout Description and GenerationI-Lun Tseng, Adam Postula. 661-672 [doi]
• SDL and Timed Petri Nets versus UPPAAL for the validation of embedded architecture in automotiveKaren Godary, Isabelle Augé-Blum, Anne Mignotte. 672-684 [doi]