Table of Contents

• The application of Aspectual Feature Module in the development and verification of SystemC modelsJun Ye, Tun Li, Qingping Tan. 1-6 [doi]
• RAT-based formal verification of QDI asynchronous controllersKhaled Alsayeg, Katell Morin-Allory, Laurent Fesquet. 1-6 [doi]
• Analysis of sense finger dynamics for accurate ΣΔ MEMS accelerometer modelling in VHDL-AMSChenxu Zhao, Tom J. Kazmierski. 1-4 [doi]
• Evaluation of SystemC-AMS modeling capabilities of RF front-end non-linearities: satellite receiver case studyRami Khouri, Benjamin Nicolle, Luca Alves Da Silva, William Tatinian, Gilles Jacquemod. 1-4 [doi]
• Another take on functional system-level design and modelingTomasz Toczek, Dominique Houzet, Stéphane Mancini. 1-6 [doi]
• DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL codeH. Gregor Molter, André Seffrin, Sorin Alexander Huss. 1-6 [doi]
• Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specificationsFernando Herrera, Eugenio Villar. 1-6 [doi]
• A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chipAlain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius. 1-4 [doi]
• Semi-automated Hw/Sw Co-design for embedded systems: from MARTE models to SystemC simulatorsLuis Gabriel Murillo, Marcello Mura, Mauro Prevostini. 1-6 [doi]
• Checkpoint and Restore for SystemC modelsMarius Monton, Jakob Engblom, Mark Burton. 1-6 [doi]
• Fast and unified SystemC AMS - HDL simulationYaseen Zaidi, Christoph Grimm, Jan Haase. 1-6 [doi]
• Proposal to extend frequency domain analysis in VHDL-AMSJoachim Haase, Ewald Hessel, Heinz-Theo Mammen. 1-4 [doi]
• A SystemC TLM2 model of communication in wormhole switched Networks-On-ChipAdán Kohler, Martin Radetzki. 1-4 [doi]
• Transaction level modeling of an adaptive multi-standard and multi-application radio communication systemAnthony Barreteau, Sébastien LeNours, Olivier Pasquier, Jean Paul Calvez. 1-6 [doi]
• EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applicationsBijoy A. Jose, Jason Pribble, Lemaire Stewart, Sandeep K. Shukla. 1-6 [doi]
• Efficient approximately-timed performance modeling for architectural exploration of MPSoCsMartin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich. 1-6 [doi]
• A top-down approach for the design of low-power microsensor nodes for wireless sensor networkGuillaume Terrasson, Renaud Briand, Skandar Basrour, Valérie Dupé. 1-6 [doi]
• Extension of SystemC framework towards power analysisMassimo Conti, Giovanni B. Vece, Sara Colazilli. 1-4 [doi]
• A re-use methodology for formal SoC protocol compliance verificationMinh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann. 1-6 [doi]
• Transaction level modeling of a FlexRay communication networkM. Cheikhwafa, Sébastien LeNours, Olivier Pasquier, Jean Paul Calvez. 1-4 [doi]
• A VHDL-AMS modeling methodology for top-down/bottom-up design of RF systemsTorsten Mähne, Alain Vachoux, Frédéric Giroud, Matteo Contaldo. 1-7 [doi]
• Exploration of embedded memories in SoCs using SystemC-based functional performance modelsHans Peter Löb, Christian Sauer. 1-6 [doi]
• SMT-based stimuli generation in the SystemC Verification libraryRobert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler. 1-6 [doi]
• HSPICE implementation of a numerically efficient model of CNT transistorTom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi. 1-5 [doi]
• SystemC-based power simulation of wireless sensor networksJan Haase, Markus Damm, Johann Glaser, Javier Moreno, Christoph Grimm. 1-4 [doi]
• Design of experiments for effective pre-silicon verification of automotive electronicsMonica Rafaila, Christoph Decker, Georg Pelz, Christian Grimm. 1-6 [doi]
• Optimizing HW/SW Co-simulation based on run-time model switchingMichael Karner, Christian Steger, Reinhold Weiss, Eric Armengaud. 1-6 [doi]
• Mixed simulation kernels for high performance virtual platformsMarius Monton, Jordi Carrabina, Mark Burton. 1-6 [doi]
• Understanding physical models in VHDL-AMSAbdulhadi Shoufan, Sorin Alexander Huss. 1-4 [doi]
• ISIS: Runtime verification of TLM platformsLuca Ferro, Laurence Pierre. 1-6 [doi]
• Linking GENESYS application architecture modelling with platform performance simulationSubayal Khan, Susanna Pantsar-Syväniemi, Jari Kreku, Kari Tiensyrjä, Juha-Pekka Soininen. 1-6 [doi]
• Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesisMarko Rossler, Hailu Wang, Ulrich Heinkel, Nur Engin, Wolfram Drescher. 1-6 [doi]
• High level synthesis using operation propertiesJan Langer, Ulrich Heinkel. 1-6 [doi]
• Design automation model for application-specific processors on reconfigurable fabricBayram Kurumahmut, Gokhan Kabukcu, Roza Ghamari, Arda Yurdakul. 1-6 [doi]
• A SystemC superset for high-level synthesisMaxim Smirnov, Andres Takach. 1-6 [doi]
• IP-XACT components with abstract time characterizationAamir Mehut Khan, Frédéric Mallet, Charles André, Robert de Simone. 1-6 [doi]
• Reuse of a HW/SW coverification environment during the refinement process of a functional C model down to an executable HW/SW specificationMarkus Winterholer, Florian Schäfer. 1-4 [doi]