Abstract is missing.
- LRoute: a delay minimal router for hierarchical CPLDsK. K. Lee, D. F. Wong. 12-20 [doi]
- A crosstalk-aware timing-driven router for FPGAsSteven J. E. Wilton. 21-28 [doi]
- Runtime and quality tradeoffs in FPGA placement and routingChandra Mulpuri, Scott Hauck. 29-36 [doi]
- Performance-driven mapping for CPLD architecturesDeming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang. 39-47 [doi]
- Simultaneous logic decomposition with technology mapping in FPGA designsGang Chen, Jason Cong. 48-55 [doi]
- Using sparse crossbars within LUTGuy G. Lemieux, David M. Lewis. 59-68 [doi]
- Detailed routing architectures for embedded programmable logic IP coresPeter Hallschmid, Steven J. E. Wilton. 69-74 [doi]
- Mixing buffers and pass transistors in FPGA routing architecturesMike Sheng, Jonathan Rose. 75-84 [doi]
- Reprogrammable network packet processing on the field programmable port extender (FPX)John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor. 87-93 [doi]
- Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipeliningPawel Chodowiec, Po Khuon, Kris Gaj. 94-102 [doi]
- Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardwareMike Estlick, Miriam Leeser, James Theiler, John J. Szymanski. 103-110 [doi]
- Is marriage in the cards for programmable logic, microprocessors and ASICs?Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta. 111 [doi]
- Attacking the semantic gap between application programming languages and configurable hardwareGreg Snider, Barry Shackleford, Richard J. Carter. 115-124 [doi]
- Matching and searching analysis for parallel hardware implementation on FPGAsPablo Moisset, Pedro C. Diniz, Joonseok Park. 125-133 [doi]
- Evaluation of the streams-C C-to-FPGA compiler: an applications perspectiveJanette Frigo, Maya Gokhale, Dominique Lavenier. 134-140 [doi]
- The effect of reconfigurable units in superscalar processorsJorge E. Carrillo, Paul Chow. 141-150 [doi]
- Interconnect pipelining in a throughput-intensive FPGA architectureAmit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska. 153-160 [doi]
- The case for registered routing switches in field programmable gate arraysDeshanand P. Singh, Stephen Dean Brown. 161-169 [doi]
- Configuration compression for FPGA-based embedded systemsAndreas Dandalis, Viktor K. Prasanna. 173-182 [doi]
- A memory coherence technique for online transient error recovery of FPGA configurationsWei-Je Huang, Edward J. McCluskey. 183-192 [doi]
- Run-Time defect tolerance using JBitsPrasanna Sundararajan, Steve Guccione. 193-198 [doi]
- A pipelined architecture for partitioned DWT based lossy image compression using FPGA sJörg Ritter, Paul Molitor. 201-206 [doi]
- An FPGA-based video compressor for H.263 compatible bit streamsGerhard Lienhart, Reinhard Männer, K. H. Noffz, R. Lay. 207-212 [doi]