Abstract is missing.
- Interconnect enhancements for a high-speed PLD architectureMichael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev. 3-10 [doi]
- FPGA switch block layout and evaluationHerman Schmit, Vikas Chandra. 11-18 [doi]
- Circuit design of routing switchesGuy G. Lemieux, David M. Lewis. 19-28 [doi]
- A faster distributed arithmetic architecture for FPGAsRadhika S. Grover, Weijia Shang, Qiang Li. 31-39 [doi]
- Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logicAlan Daly, William P. Marnane. 40-49 [doi]
- A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPsJ. Dido, N. Geraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier. 50-55 [doi]
- Efficient circuit clustering for area and power reduction in FPGAsAmit Singh, Malgorzata Marek-Sadowska. 59-66 [doi]
- Integrated retiming and placement for field programmable gate arraysDeshanand P. Singh, Stephen Dean Brown. 67-76 [doi]
- SPFD-based global rewiringJason Cong, Yizhou Lin, Wangning Long. 77-84 [doi]
- EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuitsWilliam Chow, Jonathan Rose. 85-94 [doi]
- FPGA implementation of neighborhood-of-four cellular automata random number generatorsBarry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider. 106-112 [doi]
- Cryptographic rights management of FPGA intellectual property coresTom Kean. 113-118 [doi]
- Constrained clock shifting for field programmable gate arraysDeshanand P. Singh, Stephen Dean Brown. 121-126 [doi]
- Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA seriesIan Robertson, James Irvine, Patrick Lysaght, David Robinson. 127-135 [doi]
- FPGA test time reduction through a novel interconnect testing schemeStuart McCracken, Zeljko Zilic. 136-144 [doi]
- On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniquesAndy Yan, Rebecca Cheng, Steven J. E. Wilton. 147-156 [doi]
- Dynamic power consumption in Virtex[tm]-II FPGA familyLi Shang, Alireza Kaviani, Kusuma Bathala. 157-164 [doi]
- Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chipShawn Phillips, Scott Hauck. 165-173 [doi]
- Performance-constrained pipelining of software loops onto reconfigurable hardwareGreg Snider. 177-186 [doi]
- Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentationZhiyuan Li, Scott Hauck. 187-195 [doi]
- Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machineYury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon. 196-205 [doi]
- Incremental reconfiguration of multi-FPGA systemsK. K. Lee, D. F. Wong. 206-213 [doi]
- Parallel-beam backprojection: an FPGA implementation optimized for medical imagingSrdjan Coric, Miriam Leeser, Eric Miller, Marc Trepanier. 217-226 [doi]
- A dynamically reconfigurable adaptive viterbi decoderSriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson. 227-236 [doi]
- Data reorganization engines for the next generation of system-on-a-chip FPGAsPedro C. Diniz, Joonseok Park. 237-244 [doi]