Abstract is missing.
- Designing with extreme parallelismGuy G. Lemieux, Tarek A. El-Ghazawi. 1-2 [doi]
- Architecture-specific packing for virtex-5 FPGAsTaneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal. 5-13 [doi]
- High-quality, deterministic parallel placement for FPGAs on commodity hardwareAdrian Ludwin, Vaughn Betz, Ketan Padalia. 14-23 [doi]
- Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spiralsKeith So. 24-34 [doi]
- Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAsMichael T. Frederick, Arun K. Somani. 37-46 [doi]
- WireMap: FPGA technology mapping for improved routabilityStephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko. 47-55 [doi]
- Mapping for better than worst-case delays in LUT-based FPGA designsKirill Minkovich, Jason Cong. 56-64 [doi]
- Lithographic aerial image simulation with FPGA-based hardwareaccelerationJason Cong, Yi Zou. 67-76 [doi]
- A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAsEric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai. 77-86 [doi]
- A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAsMichael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer. 87-96 [doi]
- Efficient ASIP design for configurable processors with fine-grained resource sharingQuang Dinh, Deming Chen, Martin D. F. Wong. 99-106 [doi]
- Pattern-based behavior synthesis for FPGA resource reductionJason Cong, Wei Jiang. 107-116 [doi]
- C is for circuits: capturing FPGA circuits as sequential code for portabilityScott Sirowy, Greg Stitt, Frank Vahid. 117-126 [doi]
- Extreme parallel architectures for the massesTarek A. El-Ghazawi, Guy G. Lemieux. 127-128 [doi]
- TORCH: a design tool for routing channel segmentation in FPGAsMingjie Lin, Abbas El Gamal. 131-138 [doi]
- Modeling routing demand for early-stage FPGA architecture developmentWei Mark Fang, Jonathan Rose. 139-148 [doi]
- Area and delay trade-offs in the circuit and architecture design of FPGAsIan Kuon, Jonathan Rose. 149-158 [doi]
- Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliabilityLerong Cheng, Yan Lin, Lei He. 159-168 [doi]
- A novel FPGA logic block for improved arithmetic performanceHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. 171-180 [doi]
- Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAsAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne. 181-190 [doi]
- The amorphous FPGA architectureMingjie Lin. 191-200 [doi]
- Reconfigurable computing for learning Bayesian networksNarges Bani Asadi, Teresa H. Y. Meng, Wing H. Wong. 203-211 [doi]
- HybridOS: runtime support for reconfigurable acceleratorsJohn H. Kelm, Steven S. Lumetta. 212-221 [doi]
- Vector processing as a soft-core CPU acceleratorJason Yu, Guy Lemieux, Christopher Eagleston. 222-232 [doi]
- FPGA-optimised high-quality uniform random number generatorsDavid B. Thomas, Wayne Luk. 235-244 [doi]
- A hardware framework for the fast generation of multiple long-period random number streamsIshaan L. Dalal, Deian Stefan. 245-254 [doi]
- Efficient tiling patterns for reconfigurable gate arraysSumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley. 257 [doi]
- Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAsYuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera. 257 [doi]
- FPGA interconnect design using logical effortHaile Yu, Yuk Hei Chan, Philip Heng Wai Leong. 257 [doi]
- A type system for static typing of a domain-specific languagePaul E. McKechnie, Nathan A. Lindop, Wim Vanderbauwhede. 258 [doi]
- High-throughput interconnect wave-pipelining for global communication in FPGAsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. 258 [doi]
- Measuring and modeling FPGA clock variabilityN. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung. 258 [doi]
- Configurable decoders with application in fast partial reconfiguration of FPGAsMatthew Collin Jordan, Ramachandran Vaidyanathan. 259 [doi]
- When FPGAs are better at floating-point than microprocessorsFlorent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran. 260 [doi]
- Efficient FPGA implementation of qr decomposition using a systolic array architectureXiaojun Wang, Miriam Leeser. 260 [doi]
- An integrated debugging environment for FPGA computing platformsKevin Camera, Robert W. Brodersen. 260 [doi]
- CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architecturesAndrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan. 261 [doi]
- Retrieving 3-d information with FPGA-based stream processingHidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri. 261 [doi]
- Communication bottleneck in hardware-software partitioningMaryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh. 262 [doi]
- FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motorsJose de Jesus Rangel-Magdaleno, René de Jesús Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez. 263 [doi]
- FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machineryLuis Miguel Contreras-Medina, René de Jesús Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz. 263 [doi]
- Implementing high-speed string matching hardware for network intrusion detection systemsAtul Mahajan, Benfano Soewito, Sai K. Parsi, Ning Weng, Haibo Wang. 264 [doi]
- Fpga-based data acquisition system for a positron emission tomography (PET) scannerMichael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck. 264 [doi]
- From the bitstream to the netlistJean-Baptiste Note, Éric Rannaud. 264 [doi]
- A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware designDavid Sheldon, Frank Vahid. 264 [doi]
- Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trainsAmin Ansari, Keyvan Amiri. 265 [doi]