Abstract is missing.
- New CAD Framework Extends Simulation of Dynamically Reconfigurable LogicDavid Robinson, Gordon McGregor, Patrick Lysaght. 1-8 [doi]
- Pebble: A Language for Parametrised and Reconfigurable Hardware DesignWayne Luk, Steve McKeever. 9-18 [doi]
- Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAsValery Sklyarov, Ricardo Sal Monteiro, Nuno Lau, Andreia Melo, Arnaldo Oliveira, Konstantin Kondratjuk. 19-28 [doi]
- Designing for Xilinx XC6200 FPGAsReiner W. Hartenstein, Michael Herz, Frank Gilbert. 29-38 [doi]
- Perspectives of Reconfigurable Computing in Research, Industry and EducationJürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner. 39-48 [doi]
- Field-Programmable Logic: Catalyst for New Computing ParadigmsGordon J. Brebner. 49-58 [doi]
- Run-Time Management of Dynamically Recongigurable DesignsNabeel Shirazi, Wayne Luk, Peter Y. K. Cheung. 59-68 [doi]
- Acceleration of Satisfiability Algorithms by Reconfigurable HardwareMarco Platzner, Giovanni De Micheli. 69-78 [doi]
- An Optimized Design Flow for Fast FPGA-Based Rapid PrototypingJörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke. 79-88 [doi]
- A Knowledge-Based System for Prototyping on FPFAsHelena Krupnova, Vu DucAnh Dinh, Gabriele Saucier. 89-98 [doi]
- JVX - A Rapid Prototyping System Based on Java and FPGAsRobert Macketanz, Wolfgang Karl. 99-108 [doi]
- Prototyping New ILP Architectures Using FPGAsJoy Shetler, Brian Hemme, Chia Yang, Christopher Hinsz. 109-118 [doi]
- CAD System for ASM and FSM SynthesisSamary Baranov. 119-128 [doi]
- Fast Floorplanning for FPGAsJohn M. Emmert, Akash Randhar, Dinesh Bhatia. 129-138 [doi]
- SRAM-Based FPGAs: A Fault Model for the Configurable Logig ModulesMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 139-148 [doi]
- Reconfigurable Hardware as Shared Resource in Multipurpose ComputersGunter Haug, Wolfgang Rosenstiel. 149-158 [doi]
- Reconfigurable Computer Array: The Bridge between High Speed Sensors and Low Speed ComputingScott H. Robinson, Michael P. Chaffrey, Mark E. Dunham. 159-168 [doi]
- A Reconfigurable Engine for Real-Time Video ProcessingWayne Luk, P. Andreou, Arran Derbyshire, F. Dupont-De-Dinechin, J. Rice, Nabeel Shirazi, D. Siganos. 169-178 [doi]
- An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic ApplicationsFrank-Michael Renner, Jürgen Becker, Manfred Glesner. 179-188 [doi]
- Exploiting Contemporary Memory Techniques in Reconfigurable AcceleratorsReiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger. 189-198 [doi]
- Self Modifying Circuitry - A Platform for Tractable Virtual CircuitryAdam Donlin. 199-208 [doi]
- REACT: Reactive Environment for Runtime ReconfigurationDinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna. 209-217 [doi]
- Evaluation of the XC6200-series Architecture for Cryptographic ApplicationsStephen Charlwood, Philip James-Roxby. 218-227 [doi]
- An FPFA Based Object Recognition MachineAli Zakerolhosseini, Peter Lee, Ed Horne. 228-237 [doi]
- PCI-SCI Protocol Translations: Applying Microprogramming Concepts to FPGAsGeorg Acher, Wolfgang Karl, Markus Leberecht. 238-247 [doi]
- Instruction-Level Parallelism for Reconfigurable ComputingTimothy J. Callahan, John Wawrzynek. 248-257 [doi]
- A Hardwar/Software Co-design Environment for Reconfigurable Logic SystemsGordon McGregor, David Robinson, Patrick Lysaght. 258-267 [doi]
- Mapping Loops onto Reconfigurable ArchitecturesKiran Bondalapati, Viktor K. Prasanna. 268-277 [doi]
- Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design ExperienceSameh W. Asaad, Kevin W. Warren. 278-287 [doi]
- High-Level Synthesis for Dynamically Reconfigurable Hardware/Software SystemsRainer Kress, Andreas Pyttel. 288-297 [doi]
- Dynamic Specialisation of XC6200 FPGAs by Parial EvaluationNicholas McKay, Satnam Singh. 298-307 [doi]
- WebScope: A Circuit Debug ToolSteve Guccione. 308-315 [doi]
- Computing Goldbach Partitions Using Pseudo-random Bit Generator Operators on a FPFA Systolic ArrayDominique Lavenier, Yannick Saouter. 316-325 [doi]
- Solving Boolean Satisfiability with Dynamic Hardware ConfigurationsPeixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik. 326-335 [doi]
- Modular Exponent Realization on FPGAsJuri Põldre, Kalle Tammemäe, Marek Mandre. 336-347 [doi]
- Cost Effective 2×2 Inner Product ProcessorsBéla Fehér, Gábor Szedö. 348-355 [doi]
- A Field-Programmable Gate-Array System for Evolutionary ComputationTsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino. 356-365 [doi]
- A Transmutable Telecom SystemToshiaki Miyazaki, Kazuhiro Shirakawa, Masaru Katayama, Takahiro Murooka, Atsushi Takahara. 366-375 [doi]
- A Survey of Reconfigurable Computing ArchitecturesBozidar Radunovic, Veljko M. Milutinovic. 376-385 [doi]
- A Novel Field Programmable Gat Array Architecture for High Speed Arithmetic ProcessingN. L. Miller, Steven F. Quigley. 386-390 [doi]
- Accelerating DTP with Reconfigurable Computing EnginesDonald MacVicar, Satnam Singh. 391-395 [doi]
- Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and ComputationsCarmen N. Ojeda-Guerra, Roberto Esper-Chaín, M. Estupiñán, Elsa M. Macías, Álvaro Suárez. 396-400 [doi]
- An Interactive Datasheet for the Xilinx XC6200Gordon J. Brebner. 401-405 [doi]
- Fast Adaptive Image Processing in FPGAs Using Stack FiltersNeil Woolfries, Patrick Lysaght, Stephen Marshall, Gordon McGregor, David Robinson. 406-410 [doi]
- Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic ArraysSergej Sawitzki, Achim Gratz, Rainer G. Spallek. 411-415 [doi]
- A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable LogicNeil W. Bergmann, Peter R. Sutton. 416-420 [doi]
- Maestro-Link: A High Performance Interconnect for PC ClusterShinichi Yamagiwa, Masaaki Ono, Takeshi Yamazaki, Pusit Kulkasem, Masayuki Hirota, Koichi Wada. 421-425 [doi]
- A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI ArchitectureTsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Ryusuke Konishi, Norbert Imlig. 426-430 [doi]
- A Hardwar Operating System for Dynamic Reconfiguration of FPGAsPedro Merino, Juan Carlos López, Margarida F. Jacome. 431-435 [doi]
- High Speed Low Level Image Processing on FPGAs Using Distributed ArithmeticElena Cerro-Prada, Philip James-Roxby. 436-440 [doi]
- A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAsTien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch. 441-445 [doi]
- Implementing Processor Arrays on FPGAsIstván Vassányi. 446-450 [doi]
- Reconfigurable Hardware - A Study in CodesignSamuel Holmström, Kaisa Sere. 451-455 [doi]
- Statechart-Based HW/SW-Codesign of a Multi-FPGA-Board and a MicroprocessorClaude Ackad. 456-460 [doi]
- Simulation of ATM Switches Using Dynamically Reconfigurable FPGAsAbdellah Touhafi, Wouter Brissinck, Erik F. Dirkx. 461-465 [doi]
- Fast Prototyping Using System EmulatorsTero Rissa, Tommi Mäkeläinen, Jarkko Niittylahti, Jouni Siirtola. 466-470 [doi]
- Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained ArchitecturesAndreas Dandalis, Viktor K. Prasanna. 471-475 [doi]
- XILINX4000 Architecture-Driven Synthesis for SpeedIgor Lemberski, M. Ratniece. 476-480 [doi]
- The PLD-Implementation of Boolean Function Characterized by Minimum DelayValeri Tomachev. 481-484 [doi]
- Reconfigurable PCI-Bus Interface (RPCI)A. Abo Shosha, P. Reinhart, F. Rongen. 485-489 [doi]
- Programmabel Prototyping System for Image ProcessingAndrej Trost, Andrej Zemva, Baldomir Zajc. 490-494 [doi]
- A Co-simulation Concept for an Efficient Analysis of Complex Logic DesignsJ. Fischer, C. Müller, H. Kurz. 495-499 [doi]
- Programming and Implementation of Reconfigurable RoutersAndreas C. Döring, Wolfgang Obelöer, Gunther Lustig. 500-504 [doi]
- Virtual Instruments Based on Reconfigurable LogicMaría José Moure, María Dolores Valdés, Enrique Mandado. 505-509 [doi]
- The >S<puter: Introducing a Novel Concept for Dispatching Instructions Using Reconfigurable HardwareChristian Siemers, Dietmar P. F. Möller. 510-514 [doi]
- A 6200 Model and Editor Based on Object TechnologyLoïc Lagadec, Bernard Pottier. 515-519 [doi]
- Interfacing Hardware and SoftwareMichael Eisenring, Jürgen Teich. 520-524 [doi]
- Generating Layouts for Self-implementing ModulesJames Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig. 525-529 [doi]