Table of Contents

• The Intel Geneseo ProjectAjay V. Bhatt. 1 [doi]
• System-Level Design for FPGAsMark Dickinson. 2 [doi]
• Adventures with a Reconfigurable Research PlatformJohn Wawrzynek. 3 [doi]
• Redefining the FPGA for the Next GenerationSteve Trimberger. 4 [doi]
• Design Space Exploration of the European Option Benchmark Using HyperStreamsGareth W. Morris, Matthew Aubury. 5-10 [doi]
• Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable ComputerJahyun J. Koo, Alan Evans, Warren J. Gross. 11-16 [doi]
• Soft-Hard 3D FD-TD Solver for Non Destructive EvaluationFernando Pardo, P. López, Diego Cabello. 17-22 [doi]
• Array Synthesis in SystemC Hardware CompilationJohan Ditmar, Steve McKeever. 23-28 [doi]
• Floating-Point Trigonometric Functions for FPGAsJérémie Detrey, Florent de Dinechin. 29-34 [doi]
• A Method for Fast Hardware Specialization at run-timeKarel Bruneel, Peter Bertels, Dirk Stroobandt. 35-40 [doi]
• A Many-core Implementation based on the Reconfigurable Mesh ModelHeiner Giefers, Marco Platzner. 41-46 [doi]
• An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor SystemsTaeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee. 47-53 [doi]
• RAMP Blue: A Message-Passing Manycore System in FPGAsAlex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz. 54-61 [doi]
• A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGALudovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Bart Kincaid. 62-67 [doi]
• TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable PlatformsJungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijay Narayanan, K. Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun. 68-73 [doi]
• Performance Modeling of 2D Cellular Automata on FPGAS. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot. 74-78 [doi]
• Bringing High-Performance Reconfigurable Computing to Exact ComputationsEsam El-Araby, Ivan Gonzalez, Tarek A. El-Ghazawi. 79-85 [doi]
• Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based SystemsYi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris. 86-91 [doi]
• Multi-processor System-level Synthesis for Multiple Applications on Platform FPGAAkash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal. 92-97 [doi]
• Supporting High Level Language Semantics Within Hardware Resident ThreadsErik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews. 98-103 [doi]
• Formal Modeling of Process MigrationAric D. Blumer, Henning S. Mortveit, Cameron D. Patterson. 104-110 [doi]
• Dynamic Cache Switching in Reconfigurable Embedded SystemsJohn Shield, Peter Sutton, Philip Machanick. 111-116 [doi]
• Improving Timing-Driven FPGA Packing With Physical InformationDoris T. Chen, Kristofer Vorwerk, Andrew A. Kennings. 117-123 [doi]
• Clock-Aware Placement for FPGAsJulien Lamoureux, Steven J. E. Wilton. 124-131 [doi]
• Fast On-line Task Placement and Scheduling on Reconfigurable DevicesXuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng. 132-138 [doi]
• A Hardware Algorithm for the Minimum p-Quasi Clique Cover ProblemShuichi Watanabe, Junji Kitamichi, Kenichi Kuroda. 139-144 [doi]
• High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequencesYoshiki Yamaguchi, Tsutomu Maruyama, Fumikazu Konishi, Akihiko Konagaya. 145-150 [doi]
• Discrete Event Simulation of Molecular Dynamics with Configurable LogicJosh Model, Martin C. Herbordt. 151-158 [doi]
• Pre-route Interconnect Capacitance and Power Estimation in FPGAsShilpa Bhoj, Dinesh Bhatia. 159-164 [doi]
• Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable SystemsPao-Ann Hsiung, Chih-Wen Liu. 165-170 [doi]
• A Power Estimation Model for an FPGA-based Softcore ProcessorPeter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll. 171-176 [doi]
• A Software Defined Radio Application Utilizing Modern FPGAs and NoC InterconnectsGraham Schelle, Jeff Fifield, Dirk Grunwald. 177-182 [doi]
• Intellectual Property Protection of HDL IP Cores Through Automated Sognature HostingEncarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz. 183-188 [doi]
• Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP ProtectionJorge Guajardo, Sandeep Kumar, Geert Jan Schrijen, Pim Tuyls. 189-195 [doi]
• Domain-Specific Hybrid FPGA: Architecture and Floating Point ApplicationsChun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton. 196-201 [doi]
• Embedded Programmable Logic Core Enhancements for System Bus InterfacesBradley R. Quinton, Steven J. E. Wilton. 202-209 [doi]
• Improving Pipelined Soft Processors with MultithreadingMartin Labrecque, J. Gregory Steffan. 210-215 [doi]
• An area-efficient alternative to adaptive median filtering in FPGAsZdenek Vasícek, Lukás Sekanina. 216-221 [doi]
• An Efficient Implementation of a 2D DWT on FPGAMichael Wisdom, Peter Lee. 222-227 [doi]
• H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based ArchitectureAdam Major, Ioannis Nousias, Sami Khawam, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan. 228-233 [doi]
• On the feasibility of early routing capacitance estimation for FPGAsJonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung. 234-239 [doi]
• Power Reduction in Network Equipment through Adaptive Partial ReconfigurationJuanjo Noguera, Irwin O. Kennedy. 240-245 [doi]
• Adaptive Thermoregulation for Applications on Reconfigurable DevicesPhillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood. 246-253 [doi]
• FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction MethodMasato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano. 254-259 [doi]
• GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA ChainsOctavian Cret, Zsolt Mathe, Paul Ciobanu, Sonia Marginean, Cristian Lelutiu. 260-266 [doi]
• A Unified Streaming Architecture for Real Time Face Detection and Gender ClassificationKevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy. 267-272 [doi]
• Disjoint Pattern Enumeration for Custom Instructions IdentificationPan Yu, Tulika Mitra. 273-278 [doi]
• Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis ToolsChee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha. 279-284 [doi]
• An Execution Model for Hardware/Software Compilation and its System-Level RealizationHolger Lange, Andreas Koch. 285-292 [doi]
• Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA DevicesShannon Koh, Oliver Diessel. 293-298 [doi]
• Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro DevicesRashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara. 299-304 [doi]
• A generalized and unified SPFD-based rewiring techniquePongstorn Maidee, Kia Bazargan. 305-310 [doi]
• Improving External Memory Access for Avalon Systems on Programmable Chips.Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt. 311-316 [doi]
• Time Predictable CPU and DMA Shared Memory AccessChristof Pitter, Martin Schoeberl. 317-322 [doi]
• Virtualization on the Tartan Reconfigurable ArchitectureMahim Mishra, Seth Copen Goldstein. 323-330 [doi]
• A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAsJens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann. 331-338 [doi]
• Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97)Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann. 339-344 [doi]
• Efficient mapping of a Kalman filter into an FPGA using Taylor ExpansionYang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung. 345-350 [doi]
• Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAsKatarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker. 351-356 [doi]
• L4: An FPGA-Based Accelerator for Detailed Maze RoutingJohn A. Nestor, Jeremy Lavine. 357-362 [doi]
• Improving Annealing Via Directed MovesKristofer Vorwerk, Andrew A. Kennings, Jonathan Greene, Doris T. Chen. 363-370 [doi]
• artNoC - A Novel Multi-Functional Router Architecture for Organic ComputingChristian Schuck, Stefan Lamparth, Jürgen Becker. 371-376 [doi]
• A Time-Triggered Network-on-ChipMartin Schoeberl. 377-382 [doi]
• A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable SystemsDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano. 383-388 [doi]
• Router Design for Application Specific Networks-on-Chip on Reconfigurable SystemsMário P. Véstias, Horácio C. Neto. 389-394 [doi]
• The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous SystemsAndreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, F. Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, M. Martinez. 396-401 [doi]
• HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL GenerationKoen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis. 402-408 [doi]
• MORPHEUS: Heterogeneous Reconfigurable ComputingFlorian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker. 409-414 [doi]
• On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER ProjectKatarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat. 415-422 [doi]
• Equivalence Verification of FPGA and Structured ASIC ImplementationsJoachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam. 423-428 [doi]
• Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAsSatish Sivaswamy, Kia Bazargan. 429-434 [doi]
• Fault Models and Yield Analysis for QCA-based PLAsMichael Crocker, Michael T. Niemier, Xiaobo Sharon Hu. 435-440 [doi]
• ReconOS: An RTOS supporting Hard- and Software ThreadsEnno Lübbers, Marco Platzner. 441-446 [doi]
• The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed ArchitecturesWei Han, Ioannis Nousias, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan. 447-452 [doi]
• Monte Carlo Logarithmic Number System for Model Predictive ControlPanagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold, Mayuresh V. Kothare. 453-458 [doi]
• Dynamic Voltage Scaling in a FPGA-based System-on-ChipJosé L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler. 459-462 [doi]
• Multiplexer-based routing fabric for reconfigurable logicMartijn T. Bennebroek, Alexander Danilin. 463-466 [doi]
• H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable ArchitectureMahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker. 467-471 [doi]
• Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization AlgorithmsRoberto Gutierrez, Javier Valls. 472-475 [doi]
• Efficient Priority-Queue Data Structure for Hardware ImplementationAndrew Morton, Jeffrey Liu, Insop Song. 476-479 [doi]
• Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number GenerationRalf Laue 0002, Oliver Kelm, Sebastian Schipp, Abdulhadi Shoufan, Sorin A. Huss. 480-484 [doi]
• Design of a hardware accelerator for fingerprint alignmentMariano Fons, Francisco Fons, Enrique Cantó, Mariano López. 485-488 [doi]
• An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman MethodShingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya. 489-492 [doi]
• An FPGA Solver for Very Large SAT ProblemsKenji Kanazawa, Tsutomu Maruyama. 493-496 [doi]
• A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable ArraysIoannis Nousias, Sami Khawam, Mark Milward, Mark Muir, Tughrul Arslan. 497-500 [doi]
• Aggressive Loop Pipelining for Reconfigurable ArchitecturesRicardo Menotti, Eduardo Marques, João M. P. Cardoso. 501-502 [doi]
• Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation TechniqueHagen Gädke, Andreas Koch. 503-504 [doi]
• Self-Healing Circuits for Space-ApplicationsThomas Panhofer, Martin Delvai. 505-506 [doi]
• Automatic Software Hardware Co-Design for Reconfigurable Computing SystemsProshanta Saha. 507-508 [doi]
• VPH - A Tool for Exploring Hybrid FPGAsChi Wai Yu. 509-510 [doi]
• Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from CJim Stevens. 511-512 [doi]
• Wires On Demand: Run-Time Communication Synthesis for Reconfigurable ComputingPeter M. Athanas, J. Bowen, T. Dunham, Cameron Patterson, J. Rice, Matthew Shelburne, J. Surís, Mark B. Bucciero, Jonathan Graf. 513-516 [doi]
• A Behavioral Synthesis Approach for Distributed Memory FPGA ArchitecturesAshutosh Pal, M. Balakrishnan. 517-520 [doi]
• Mapping A VLIWxSIMD Processor on an FPGA: Scalability and PerformanceMicha Nelissen, Kees van Berkel, Sergei Sawitzki. 521-524 [doi]
• An Automatic Compilation Framework for Configurable ArchitecturesAlberto Gallini, Lorenzo Pavesi, Claudio Ferretti, Alberto Rosti, Sara Bocchio. 525-528 [doi]
• A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithmVinay Sriram, David Kearney. 529-532 [doi]
• Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor SystemKai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid. 533-536 [doi]
• A Load/Store Unit for a Memcpy Hardware AcceleratorStamatis Vassiliadis, Filipa Duarte, Stephan Wong. 537-541 [doi]
• Incremental Fault EmulationJan Torben Weinkopf, Klaus Harbich, Erich Barke. 542-545 [doi]
• A novel motion estimation power reduction techniqueGraeme Stewart, David Renshaw, Martyn Riley. 546-549 [doi]
• A Variable Grain Logic Cell Architecture for Reconfigurable Logic CoresMotoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi. 550-553 [doi]
• A High Speed License Plate Recognition System on an FPGATakamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka. 554-557 [doi]
• REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation StructuresA. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan. 558-561 [doi]
• Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium CoreLodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit. 562-566 [doi]
• A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGAJosé M. Claver, P. Agustí, G. León, Manel Canseco. 567-570 [doi]
• C++ based design flow for reconfigurable image processing systemsRob Beun, Irek Karkowski, Maarten Ditzel. 571-575 [doi]
• A floating-point Extended Kalman Filter implementation for autonomous mobile robotsVanderlei Bonato, Eduardo Marques, George A. Constantinides. 576-579 [doi]
• Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA ChipsHristo Nikolov, Todor Stefanov, Ed F. Deprettere. 580-584 [doi]
• Hardware/Software Process Migration and RTL SimulationAric D. Blumer, Cameron D. Patterson. 585-588 [doi]
• Implementation of a barotropic operator for ocean model simulation using a reconfigurable machineSayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell. 589-592 [doi]
• Evolutionary Search Applied to Reconfigurable Analogue ControlKester Clegg, Susan Stepney, Tim Clarke. 593-596 [doi]
• Soft IP core implementation of recursive least squares filter using only multplicative and additive operatorsGaye Lightbody, Roger Woods, Jonathan Francey. 597-600 [doi]
• Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing CoresAndrew G. Schmidt, Ron Sass. 601-604 [doi]
• A Design Flow to Map Parallel Applications onto FPGAsSébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. 605-608 [doi]
• A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing ApplicationsIrfan Syed, John A. Williams, Neil W. Bergmann. 609-612 [doi]
• Novel Multi-Layer floorplanning for Heterogeneous FPGAsLove Singhal, Elaheh Bozorgzadeh. 613-616 [doi]
• Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point SystemsWilliam G. Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer. 617-620 [doi]
• Accelerating Microblaze Floating Point OperationsJiri Kadlec, Roman Bartosinski, Martin Danek. 621-624 [doi]
• Analysis of Kernel Effects on Optimisation Mismatch in Cache ReconfigurationJohn Shield, Peter Sutton, Philip Machanick. 625-628 [doi]
• High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAsJosé M. Claver, G. León. 629-632 [doi]
• Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platformsSven-Ole Voigt, Thomas Teufel. 633-637 [doi]
• RIC Fast Adder and its Set Tolerant Implementation in FPGAsEduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel. 638-641 [doi]
• Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater. 642-647 [doi]
• High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGATomas Dedek, Tomas Marek, Tomás Martínek. 648-651 [doi]
• Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool SupportKostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris. 652-655 [doi]
• AdaBoost EnginePavel Zemcík, Martin Zádník. 656-660 [doi]
• An FPGA Based Memory Efficient Shared Buffer ImplementationDwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic. 661-664 [doi]
• Efficient Modeling and Floorplanning of Embedded-FPGA FabricSumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley. 665-669 [doi]
• A New Scalable Hardware Architecture for RSA AlgorithmTamer Güdü. 670-674 [doi]
• Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 PrimitiveIrwin O. Kennedy. 675-678 [doi]
• Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-ProStefan Raaijmakers, Stephan Wong. 679-683 [doi]
• Dynamic reconfiguration management based on a distributed object modelJulio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, Juan Carlos López. 684-687 [doi]
• Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing ApplicationsLars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach. 688-691 [doi]
• An OCM based shared Memory controller for Virtex 4Bas Breijer, Filipa Duarte, Stephan Wong. 692-696 [doi]
• DWARV: DelftWorkBench Automated Reconfigurable VHDL GeneratorYana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu 0004, Stamatis Vassiliadis. 697-701 [doi]
• Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining.Antonio Jimeno-Morenilla, Antonio Martínez, Sergio Cuenca, Jose Luis Sánchez-Romero. 702-705 [doi]
• Exploiting Analog and Digital Reconfiguration for Smart Sensor InterfacingDiego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo. 706-709 [doi]
• SoPC architecture for a Key Point DetectorHarding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns. 710-713 [doi]
• A Pipeline Implementation of a Watershed Algorithm on FPGADang Ba Khac Trieu, Tsutomu Maruyama. 714-717 [doi]
• FPGA Implementation of 64-bit Exponential Function for HPCErnest Jamro, Kazimierz Wiatr, Maciej Wielgosz. 718-721 [doi]
• A Graphical Model-Level Debugger for Heterogenous Reconfigurable ArchitecturesPhilipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker. 722-725 [doi]
• A Run-time Reconfigurable Processor for Video Motion EstimationMiguel Ribeiro, Leonel Sousa. 726-729 [doi]
• Confiuartion Management in the Context of Self Adapative SystemsYvan Eustache, Jean-Philippe Diguet. 730-734 [doi]
• A Quantitative Prediction Model for Hardware/Software PartitioningRoel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis. 735-739 [doi]
• Caching in Real-time Reconfiguration Port SchedulingFlorian Dittmann, Stefan Frank. 740-744 [doi]
• Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA CompilerKristopher D. Peterson, Justin L. Tripp. 745-748 [doi]
• Wirelength Prediction for FPGAsAudip Pandit, Ali Akoglu. 749-752 [doi]
• CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAsSlavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber. 753-756 [doi]
• System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless SystemsAli Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan. 757-760 [doi]
• A resource optimized SoC Kit for FPGAsGerald Hempel, Christian Hochberger. 761-764 [doi]
• A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTPBrandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain. 765-769 [doi]
• Compression system for the phonocardiographic signalF. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martínez-Álvarez, Juan Martínez-Alajarín, Ramón Ruiz Merino. 770-773 [doi]
• RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze ProcessorZdenek Pohl, Milan Tichý. 774-777 [doi]
• NoC Implementation in FPGA Using Torus TopologyAngelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat. 778-781 [doi]
• Microarchitectural Enhancements for Configurable Multi-Threaded Soft ProcessorsRoger Moussali, Nabil Ghanem, Mazen A. R. Saghir. 782-785 [doi]
• FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM MemoryDavid Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty. 786-791 [doi]
• A Novel Event Based Simulation Algorithm for Sequential Digital Circuit SimulationKarthick Parashar, Nitin Chandrachoodan. 792-795 [doi]
• Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor ArraysYohei Hasegawa, Hideharu Amano. 796-799 [doi]
• An fpga based open source network-on-chip architectureAndreas Ehliar, Dake Liu. 800-803 [doi]
• FlowContext: Flexible Platform for Multigigabit Stateful Packet ProcessingMartin Kosek, Jan Korenek. 804-807 [doi]
• A Combining technique of rate law functions for a cost-effective reconfigurable biological simulatorHideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri. 808-811 [doi]