Abstract is missing.
- FPGA: The future platform for transforming, transporting and computing dataIvo Bolsens. 1 [doi]
- FPGAS in high energy physics experiments at CERNL. Musa. 2 [doi]
- Searching for ET with FPGA SDan Werthimer. 3 [doi]
- Keynote: High performance computing based on FPGASO. Wohlmuth. 4 [doi]
- Increasing the level of abstraction in FPGA-based designsMartin Danek, Jiri Kadlec, Roman Bartosinski, Lukas Kohout. 5-10 [doi]
- Modeling recursion data structures for FPGA-based implementationSpyridon Ninos, Apostolos Dollas. 11-16 [doi]
- A portable abstraction layer for hardware threadsEnno Lübbers, Marco Platzner. 17-22 [doi]
- Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systemsYohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda. 23-28 [doi]
- Three-stage pipeline implementation for SHA2 using data forwardingAnh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi. 29-34 [doi]
- Chosen-message SPA attacks against FPGA-based RSA hardware implementationsAtsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh. 35-40 [doi]
- Exploring FPGA network on chip implementations across various application and network loadsGraham Schelle, Dirk Grunwald. 41-46 [doi]
- Reducing interconnection cost in coarse-grained dynamic computing through multistage networkRicardo Ferreira, Marcone Laure, Mateus B. Rutzig, Antonio C. Beck, Luigi Carro. 47-52 [doi]
- NOC architecture design for multi-cluster chipsHenrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana G. S. Santos. 53-58 [doi]
- Fast and accurate resource estimation of RTL-based designs targeting FPGASPaul Schumacher, Pradip Jha. 59-64 [doi]
- Fast toggle rate computation for FPGA circuitsTomasz S. Czajkowski, Stephen Dean Brown. 65-70 [doi]
- On-the-fly attestation of reconfigurable hardwareRicardo Chaves, Georgi Kuzmanov, Leonel Sousa. 71-76 [doi]
- How fast is an FPGA in image processing?Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi. 77-82 [doi]
- A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate ArraysTheepan Moorthy, Andy Ye. 83-88 [doi]
- Real-time image super resolution using an FPGAOliver Bowen, Christos-Savvas Bouganis. 89-94 [doi]
- sFPGA - A scalable switch based FPGA architecture and design methodologyShakith Fernando, Xiaolei Chen, Yajun Ha. 95-100 [doi]
- FPGA family composition and effects of specialized blocksPongstorn Maidee, Nagib Hakim, Kia Bazargan. 101-106 [doi]
- A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGASKazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera. 107-112 [doi]
- No-break dynamic defragmentation of reconfigurable devicesSándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich. 113-118 [doi]
- ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGASDirk Koch, Christian Beckhoff, Jürgen Teich. 119-124 [doi]
- An efficient run-time router for connecting modules in FPGASJorge Suris, Cameron Patterson, Peter Athanas. 125-130 [doi]
- High-speed regular expression matching engine using multi-character NFANorio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya. 131-136 [doi]
- Scalable high-throughput SRAM-based architecture for IP-lookup using FPGAHoang Le, Weirong Jiang, Viktor K. Prasanna. 137-142 [doi]
- Mining Association Rules with systolic treesSong Sun, Joseph Zambreno. 143-148 [doi]
- A configurable and programmable motion estimation processor for the H.264 video codecJose Luis Nunez-Yanez, Eddie Hung, Vassilios Chouliaras. 149-154 [doi]
- A flexible and reliable embedded system for detector control in a high energy physics experimentTobias Krawutschke. 155-160 [doi]
- Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logicSylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst. 161-166 [doi]
- Loop unrolling and shifting for reconfigurable architecturesOzana Silvia Dragomir, Todor Stefanov, Koen Bertels. 167-172 [doi]
- CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architecturesAndrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers. 173-178 [doi]
- Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming frameworkQiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. 179-184 [doi]
- FPGA implementation of a flexible decoder for long LDPC codesChristiane Beuschel, Hans-Jörg Pfleiderer. 185-190 [doi]
- Towards an early neural circuit simulator : A FPGA implementation of processing in the rat whisker systemBrian Leung, Yan Pan, Chris Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. Hartmann. 191-196 [doi]
- Decimal multiplier on FPGA using embedded binary multipliersHorácio C. Neto, Mário P. Véstias. 197-202 [doi]
- A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processorLars Bauer, Muhammad Shafique, Jörg Henkel. 203-208 [doi]
- Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processorYoung-Su Kwon, Bontae Koo, Nak-Woong Eum. 209-214 [doi]
- Instruction buffer mode for multi-context Dynamically Reconfigurable ProcessorsToru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano. 215-220 [doi]
- An analytical model describing the relationships between logic architecture and FPGA densityAndrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk. 221-226 [doi]
- Rapid estimation of power consumption for hybrid FPGAsChun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton. 227-232 [doi]
- A technique for minimizing power during FPGA placementKristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-chung Hsu, Arun Kundu, Andrew A. Kennings. 233-238 [doi]
- Sampling from the exponential distribution using independent Bernoulli variatesDavid B. Thomas, Wayne Luk. 239-244 [doi]
- Enhancing security of ring oscillator-based trng implemented in FPGAViktor Fischer, Florent Bernard, Nathalie Bochard, Michal Varchola. 245-250 [doi]
- Digital hilbert transformers for FPGA-based phase-locked loopsMartin Kumm, M. Shahab Sanjari. 251-256 [doi]
- Metawire: Using FPGA configuration circuitry to emulate a Network-on-ChipMatthew Shelburne, Cameron Patterson, Peter Athanas, Mark Jones, Brian Martin, Ryan Fong. 257-262 [doi]
- GICS: Generic interconnection systemTamas Malek, Tomás Martínek, Jan Korenek. 263-268 [doi]
- A link removal methodology for Networks-on-Chip on reconfigurable systemsDaihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi. 269-274 [doi]
- Mapping and scheduling with task clustering for heterogeneous computing systemsYuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong. 275-280 [doi]
- Low-latency high-bandwidth HW/SW communication in a virtual memory environmentHolger Lange, Andreas Koch. 281-286 [doi]
- ATCA-based computation platform for data acquisition and triggering in particle physics experimentsMing Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen An Liu, Zhonghai Lu, Axel Jantsch. 287-292 [doi]
- An FPGA-based high-speed, low-latency trigger processor for high-energy physicsJan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth. 293-298 [doi]
- Shared reconfigurable architectures for CMPSMatthew A. Watkins, Mark J. Cianchetti, David H. Albonesi. 299-304 [doi]
- Power reduction techniques for Dynamically Reconfigurable Processor ArraysTakashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano. 305-310 [doi]
- An integrated debugging environment for FPGA computing platformsKevin Camera, Robert W. Brodersen. 311-316 [doi]
- Secure FPGA configuration architecture preventing system downgradeBenoît Badrignans, Reouven Elbaz, Lionel Torres. 317-322 [doi]
- Bitstream compression techniques for Virtex 4 FPGAsRadu Stefan, Sorin Cotofana. 323-328 [doi]
- FPGA acceleration of Monte-Carlo based credit derivative pricingAlexander Kaganov, Paul Chow, Asif Lakhany. 329-334 [doi]
- FPGA acceleration of quasi-Monte Carlo in financeNathan A. Woods, Tom VanCourt. 335-340 [doi]
- Acceleration of a production rigid molecule docking codeBharat Sukhwani, Martin C. Herbordt. 341-346 [doi]
- Fine grain reconfigurable architecturesJosef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker. 348 [doi]
- Coarse-grained reconfigurationSven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner. 349 [doi]
- Application-specific reconfigurable processorsHeiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll. 350 [doi]
- Seamless design flow for reconfigurable systemsAndreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef Rammig. 351 [doi]
- Network processorsThilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf. 352 [doi]
- Hyperreconfigurable architecturesSebastian Lange, Martin Middendorf. 353 [doi]
- Floating point datapath synthesis for FPGAsMartin Langhammer. 355-360 [doi]
- Automatic generation of run-time parameterizable configurationsKarel Bruneel, Dirk Stroobandt. 361-366 [doi]
- Generation of partial FPGA configurations at run-timeMiguel L. Silva, João Canas Ferreira. 367-372 [doi]
- Novel FPGA based Haar classifier face detection algorithm accelerationChangjian Gao, Shih-Lien Lu. 373-378 [doi]
- An FPGA-based implementation of the MINRES algorithmDavid Boland, George A. Constantinides. 379-384 [doi]
- Efficient FPGA mapping of Gilbert s algorithm for SVM training on large-scale classification problemsMarkos Papadonikolakis, Christos-Savvas Bouganis. 385-390 [doi]
- Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architecturesChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig. 391-396 [doi]
- An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementationStanislaw Deniziak, Mariusz Wisniewski. 397-402 [doi]
- Memory access parallelisation in high-level language compilation for reconfigurable adaptive computersHagen Gädke, Florian Stock, Andreas Koch. 403-408 [doi]
- Reconfigurable hardware: The holy grail of matching performance with programming productivityClaudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard. 409-414 [doi]
- Fault tolerant methods for reliability in FPGAsEdward Stott, N. Pete Sedcole, Peter Y. K. Cheung. 415-420 [doi]
- A non-volatile run-time FPGA using thermally assisted switching MRAMSYoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune. 421-426 [doi]
- The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arraysPing Chen, Andy Ye. 427-430 [doi]
- An embedded dynamically self-reconfigurable Master-Slaves MPSoC architectureKimon Karras, Elias S. Manolakos. 431-434 [doi]
- EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAsOliver A. Pfänder, Hans-Jörg Pfleiderer. 435-438 [doi]
- The hardware application platform of the hartes projectImmacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione. 439-442 [doi]
- Scalable high performance computing on FPGA clusters using message passingEoin Creedon, Michael Manzke. 443-446 [doi]
- FPGA interconnect design using logical effortHaile Yu, Yuk Hei Chan, Philip Heng Wai Leong. 447-450 [doi]
- An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOCJason Wu, John W. Williams, Neil Bergmann. 451-454 [doi]
- Operating system support for online partial dynamic reconfiguration managementMarco D. Santambrogio, Vincenzo Rana, Donatella Sciuto. 455-458 [doi]
- Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memoryMeikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha. 459-462 [doi]
- Numerical function generators using bilinear interpolationShinobu Nagayama, Tsutomu Sasao, Jon T. Butler. 463-466 [doi]
- A versatile hardware architecture for a CFAR detector based on a linear insertion sorterRoberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo. 467-470 [doi]
- Polymorphic wavelet architectures using reconfigurable hardwareAmit Pande, Joseph Zambreno. 471-474 [doi]
- Direct sigma-delta modulated signal processing in FPGAChiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng. 475-478 [doi]
- A lifting-based DWT and IDWT processor with multi-context configuration and normalization factorAndre Guntoro, Manfred Glesner. 479-482 [doi]
- Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networksJim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid. 483-486 [doi]
- A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneckClaudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi. 487-490 [doi]
- Customized Reconfigurable Interconnection Networks for multiple application SOCSHongbing Fan, Jason Ernst, Yu-Liang Wu. 491-494 [doi]
- New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approachDiana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker. 495-498 [doi]
- CVC: The C to RTL compiler for callback-based verification modelYasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki. 499-502 [doi]
- Performance optimization by track swapping on critical paths utilizing random variations for FPGASYuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera. 503-506 [doi]
- SAT-based resource binding for reducing critical path delaysKenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki. 507-510 [doi]
- BOUNCE, a new approach to measure sub-nanosecond time intervalsRalf Joost, Ralf Salomon. 511-514 [doi]
- Power efficient DSP datapath configuration methodology for FPGAStephen McKeown, Roger Woods, John McAllister. 515-518 [doi]
- IEEE802.16-2004 OFDM functions implementation on FPGAS with design explorationAhmad Sghaier, Shawki Areibi, Robert Dony. 519-522 [doi]
- An FPGA architecture for the Pagerank eigenvector problemSéamas McGettrick, Dermot Geraghty, Ciarán McElroy. 523-526 [doi]
- Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systemsAlexander Danilin, Sergei Sawitzki, Erik Rijshouwer. 527-530 [doi]
- Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGAMamoun F. Al-Mistarihi. 531-534 [doi]
- A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughputChristopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker. 535-538 [doi]
- Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPCAlmudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez. 539-542 [doi]
- Exploring compact design on high throughput coarse grained reconfigurable architecturesKazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka. 543-546 [doi]
- Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processorIzhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez. 547-550 [doi]
- A new methodology for debugging and validation of soft coresChristian Hochberger, Alexander Weiss. 551-554 [doi]
- Convergence analysis of run-time distributed optimization on adaptive systems using game theoryDiego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres. 555-558 [doi]
- MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimationXing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong. 559-562 [doi]
- Parallel hardware objects for dynamically partial reconfigurationNorbert Abel, Frederik Grüll, Nick Meier, Andreas Beyer, Udo Kebschull. 563-566 [doi]
- File system access from reconfigurable FPGA hardware processes in BORPHHayden Kwok-Hay So, Robert W. Brodersen. 567-570 [doi]
- Self-recofigurable embedded systems on Spartan-3Enrique Cantó, Francesc Fons, Mariano López. 571-574 [doi]
- An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessorJing Hu, Steven F. Quigley, Andrew Chan. 575-578 [doi]
- Creating unique identifiers on field programmable gate arrays using natural processing variationsJames W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington. 579-582 [doi]
- Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGAHaiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen. 583-586 [doi]
- A comparison of embedded reconfigurable video-processing architecturesChristopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich. 587-590 [doi]
- Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processorSyed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede. 591-594 [doi]
- Cluster architecture based on low cost reconfigurable hardwareCesar Pedraza, Emilio Castillo, Javier Castillo, Cristobal Camarero, José Luis Bosque, José I. Martínez, Rafael Menéndez de Llano. 595-598 [doi]
- A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGAAndreas Ehliar, Per Karlström, Dake Liu. 599-602 [doi]
- Comparing throughput and power consumption in both sequential and reconfigurable processorsKevin K. Liu, Charles B. Cameron, Antal A. Sarkady. 603-606 [doi]
- Data path driven waveform-like reconfigurationLars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker. 607-610 [doi]
- Active kernel monitoring to combat scheduler gaming in reconfigurable computing systemsWenyin Fu, Katherine Compton. 611-614 [doi]
- An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnectsHanyu Liu, Xiaolei Chen, Yajun Ha. 615-618 [doi]
- A hardware compilation flow for instance-specific VLIW coresMarkus Koester, Wayne Luk, Geoffrey Brown. 619-622 [doi]
- A reconfigurable accelerator for quantum computationsMichail Zampetakis, Vasilis Samoladas, Apostolos Dollas. 623-626 [doi]
- High-performance fpga-based floating-point adder with three inputsAndre Guntoro, Manfred Glesner. 627-630 [doi]
- A rate-based prefiltering approach to blast accelerationPanagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos. 631-634 [doi]
- Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfigurationDiego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-Vallvey. 635-638 [doi]
- Architecture and implementation of a Frame Aggregation Unit for optical frame-based switchingGeorge Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou. 639-642 [doi]
- A low overhead fault tolerant FPGA with new connection boxFujie Wong, Yajun Ha. 643-646 [doi]
- An optimization method of DMA transfer for a general purpose reconfigurable machineSayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell. 647-650 [doi]
- Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platformVlad Mihai Sima, Elena Moscu Panainte, Koen Bertels. 651-654 [doi]
- Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAsBetul Buyukkurt, Walid A. Najjar. 655-658 [doi]
- A dynamic temperature control simulation system for FPGAsShilpa Bhoj, Dinesh Bhatia. 659-662 [doi]
- Practical implementation of a network-based stochastic biochemical simulation system on an FPGAMasato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano. 663-666 [doi]
- Compiled hardware acceleration of Molecular Dynamics codeJason R. Villarreal, Walid A. Najjar. 667-670 [doi]
- Area optimization of bit parallel finite field multipliers with fast carry logic on FPGASGang Zhou, Li Li, Harald Michalik. 671-674 [doi]
- Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysisTim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred Schimmler. 675-678 [doi]
- Connected components analysis of streamed imagesDonald G. Bailey, Christopher T. Johnston, Ni Ma. 679-682 [doi]
- On the design parameters of runtime reconfigurable systemsThilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle. 683-686 [doi]
- Teaching FPGA system design via a remote laboratory facilityYamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass. 687-690 [doi]
- Towards benchmarking energy efficiency of reconfigurable architecturesTobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa. 691-694 [doi]
- FPGA interconnect sizing using extended logical effort modelHaile Yu. 695-696 [doi]
- Bio-inspiration helps computers: A new machineNicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. 697-698 [doi]
- Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimizationKatarina Paulsson, Michael Hübner, Jürgen Becker. 699-700 [doi]
- Thermal aware FPGA architectures and CADShilpa Bhoj. 701-702 [doi]
- Combating process variation on FPGAS with a precise at-speed delay measurement methodJustin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole. 703-704 [doi]
- Adaptive precision technique for genetic algorithmsChun Tak Chow. 705-706 [doi]
- Reconfigurable many-cores with lean interconnectHeiner Giefers. 707-708 [doi]