Table of Contents

• Customizable domain-specific computingJason Cong. 1 [doi]
• In search of agile hardwarePeter Athanas. 2 [doi]
• The evolution of architecture exploration of programmable devicesJonathan Rose. 3 [doi]
• FPGA challenges and opportunities at 40nm and beyondVaughn Betz. 4 [doi]
• Virtex-6 and Spartan-6, plus a look into the futurePeter Alfke. 5 [doi]
• MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling linkShotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano. 6-11 [doi]
• Hardware implementation of MPI_Barrier on an FPGA clusterShanyuan Gao, Andrew G. Schmidt, Ron Sass. 12-17 [doi]
• Fast critical sections via thread scheduling for FPGA-based multithreaded processorsMartin Labrecque, J. Gregory Steffan. 18-25 [doi]
• A biophysically accurate floating point somatic neuroprocessorYiWei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly. 26-31 [doi]
• CNP: An FPGA-based processor for Convolutional NetworksClément Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCun. 32-37 [doi]
• Noise impact of single-event upsets on an FPGA-based digital filterBrian H. Pratt, Michael J. Wirthlin, Michael P. Caffrey, Paul S. Graham, Keith Morgan. 38-43 [doi]
• Compiler assisted runtime task scheduling on a reconfigurable computerMojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels. 44-50 [doi]
• Data parallel FPGA workloads: Software versus hardwarePeter Yiannacouras, J. Gregory Steffan, Jonathan Rose. 51-58 [doi]
• Generating high-performance custom floating-point pipelinesFlorent de Dinechin, Cristian Klein, Bogdan Pasca. 59-64 [doi]
• Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processorsNachiket Kapre, André DeHon. 65-72 [doi]
• Exploring reconfigurable architectures for explicit finite difference option pricing modelsQiwei Jin, David B. Thomas, Wayne Luk. 73-78 [doi]
• Towards a viable out-of-order soft core: Copy-Free, checkpointed register renamingKaveh Aasaraai, Andreas Moshovos. 79-85 [doi]
• A runtime relocation based workflow for self dynamic reconfigurable systems designMarco D. Santambrogio, Massimo Morandi, Marco Novati, Donatella Sciuto. 86-91 [doi]
• An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAsMarkus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner. 92-98 [doi]
• FPGA partial reconfiguration via configuration scrubbingJonathan Heiner, Benjamin Sellers, Michael J. Wirthlin, Jeff Kalb. 99-104 [doi]
• Improving logic density through synthesis-inspired architectureJason Helge Anderson, Qiang Wang. 105-111 [doi]
• Clock gating architectures for FPGA power reductionSafeen Huda, Muntasir Mallick, Jason Helge Anderson. 112-118 [doi]
• Program-driven fine-grained power management for the reconfigurable meshHeiner Giefers, Marco Platzner. 119-125 [doi]
• Performance comparison of FPGA, GPU and CPU in image processingShuichi Asano, Tsutomu Maruyama, Yoshiki Yamaguchi. 126-131 [doi]
• Self-organizing multi-cue fusion for FPGA-based embedded imagingStefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich. 132-137 [doi]
• Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementationChristopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele. 138-145 [doi]
• An analytical model relating FPGA architecture and place and route runtimeScott Y. L. Chin, Steven J. E. Wilton. 146-153 [doi]
• Replace: An incremental placement algorithm for field programmable gate arraysDavid Leong, Guy G. Lemieux. 154-161 [doi]
• Optimal runtime reconfiguration strategies for systolic arraysArpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain. 162-167 [doi]
• A multi-FPGA architecture for stochastic Restricted Boltzmann MachinesDaniel L. Ly, Paul Chow. 168-173 [doi]
• Comparing fine-grained performance on the Ambric MPPA against an FPGABrad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis. 174-179 [doi]
• Low power techniques for Motion Estimation hardwareCaglar Kalaycioglu, Onur C. Ulusel, Ilker Hamzaoglu. 180-185 [doi]
• Coarse-grained dynamically reconfigurable architecture with flexible reliabilityDawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye. 186-192 [doi]
• A novel SRAM-based FPGA architecture for efficient TMR fault tolerance supportKonstantinos Kyriakoulakos, Dionisios N. Pnevmatikatos. 193-198 [doi]
• Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in spaceAdam Jacobs, Alan D. George, Grzegorz Cieslewski. 199-204 [doi]
• Modeling post-techmapping and post-clustering FPGA circuit depthJoydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk. 205-211 [doi]
• Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systemsMasato Inagi, Yasuhiro Takashima, Yuichi Nakamura. 212-217 [doi]
• An ASIC perspective on FPGA optimizationsAndreas Ehliar, Dake Liu. 218-223 [doi]
• Recursion in reconfigurable computing: A survey of implementation approachesIouliia Skliarova, Valery Sklyarov. 224-229 [doi]
• A comparison of FPGA and FPAA technologies for a signal processing applicationRoberto Selow, Heitor S. Lopes, Carlos R. Erig Lima. 230-235 [doi]
• A radix-8 complex divider for FPGA implementationDong Wang, Milos D. Ercegovac, Nanning Zheng. 236-241 [doi]
• Exploiting fast carry-chains of FPGAs for designing compressor treesHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. 242-249 [doi]
• Large multipliers with fewer DSP blocksFlorent de Dinechin, Bogdan Pasca. 250-255 [doi]
• Area estimation and optimisation of FPGA routing fabricsAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. 256-261 [doi]
• In field, energy-performance tunable FPGA architecturesBita Nezamfar, Mark Horowitz. 262-267 [doi]
• Static versus scheduled interconnect in Coarse-Grained Reconfigurable ArraysBrian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck. 268-275 [doi]
• A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systemsJoannis Sotiropoulos, Ioannis Papaefstathiou. 276-281 [doi]
• Design space exploration of reconfigurable systems for calculating flying object s optimal noise reduction pathsDimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos. 282-287 [doi]
• Real-time processing of local contrast enhancement on FPGAKentaro Kokufuta, Tsutomu Maruyama. 288-293 [doi]
• Enhancements to FPGA design methodology using streamingFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown. 294-301 [doi]
• General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systemsJosef Angermeier, Abdulazim Amouri, Jürgen Teich. 302-307 [doi]
• Optimising designs by combining model-based and pattern-based transformationsQiang Liu, Tim Todman, José Gabriel de F. Coutinho, Wayne Luk, George A. Constantinides. 308-313 [doi]
• sFPGA2 - A scalable GALS FPGA architecture and design methodologyRizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli. 314-319 [doi]
• Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocolDiana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker. 320-325 [doi]
• A new deadlock-free fault-tolerant routing algorithm for NoC interconnectionsSlavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda. 326-331 [doi]
• Accelerating HMMER search using FPGAToyokazu Takagi, Tsutomu Maruyama. 332-337 [doi]
• An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructureTobias Schumacher, Christian Plessl, Marco Platzner. 338-344 [doi]
• Efficient particle-pair filtering for acceleration of molecular dynamics simulationMatt Chiu, Martin C. Herbordt. 345-352 [doi]
• Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcastingFlorent Camarda, Jean-Christophe Prévotet, Fabienne Nouvel. 353-358 [doi]
• Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodesHeiko Hinkelmann, Peter Zipf, Manfred Glesner. 359-366 [doi]
• A highly scalable Restricted Boltzmann Machine FPGA implementationSang-Kyun Kim, Lawrence C. McAfee, Peter L. McMahon, Kunle Olukotun. 367-372 [doi]
• Pipeline implementation of the 128-bit block cipher CLEFIA in FPGATomasz Kryjak, Marek Gorgon. 373-378 [doi]
• Clock duplicity for high-precision timestamping in Gigabit EthernetCarles Nicolau, Dolors Sala, Enrique Cantó. 379-384 [doi]
• DPA resistance for light-weight implementations of cryptographic algorithms on FPGAsRajesh Velegalati, Jens-Peter Kaps. 385-390 [doi]
• Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysisHiren Patel, Yong C. Kim, J. Todd McDonald, LaVern A. Starman. 391-396 [doi]
• Towards a unique FPGA-based identification circuit using process variationsHaile Yu, Philip H. W. Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf. 397-402 [doi]
• IP protection in Partially Reconfigurable FPGAsKrzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz. 403-409 [doi]
• FPGA accelerating three QR decomposition algorithms in the unified pipelined frameworkYong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu. 410-416 [doi]
• FPGA-accelerated Information Retrieval: High-efficiency document filteringWim Vanderbauwhede, Leif Azzopardi, Mahmoud Moadeli. 417-422 [doi]
• A toolset for the analysis and optimization of motion estimation algorithms and processorsTrevor Spiteri, George Vafiadis, Jose Luis Nunez-Yanez. 423-428 [doi]
• Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3Enrique Cantó, Mariano Fons, Mariano López-Farcía, Rafael Ramos-Lara. 429-434 [doi]
• Building heterogeneous reconfigurable systems using threadsJason Agron, David L. Andrews. 435-438 [doi]
• Reconfiguration-based time-to-digital converter for Virtex FPGAsAngel Quiros Olozabal, Juan Manuel Barrientos-Villar, Ma de los Angeles Cifredo Chacon. 439-443 [doi]
• An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesisMario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard, Pierre Lacroix, Jean-Yves Fourniols. 444-447 [doi]
• High speed fixed point dividers for FPGAsGustavo Sutter, Jean-Pierre Deschamps. 448-452 [doi]
• A self-reconfiguring architecture supporting multiple objective functions in genetic algorithmsCharalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas, Ioannis Papaefstathiou. 453-456 [doi]
• Automatic generation of FPGA hardware accelerators using a domain specific languageRicardo Menotti, João M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques. 457-461 [doi]
• A dynamically reconfigurable parallel pixel processing systemDaniel Llamocca, Marios S. Pattichis, G. Alonzo Vera. 462-466 [doi]
• An approach to system-wide fault tolerance for FPGAsJano Gebelein, Heiko Engel, Udo Kebschull. 467-471 [doi]
• A multi-layered XML schema and design tool for reusing and integrating FPGA IPAdam Arnesen, Nathan Rollins, Michael J. Wirthlin. 472-475 [doi]
• Bitstream compression through frame removal and partial reconfigurationBenjamin Sellers, Jonathan Heiner, Michael J. Wirthlin, Jeff Kalb. 476-480 [doi]
• Operation scheduling for FPGA-based reconfigurable computersColin Yu Lin, Ngai Wong, Hayden Kwok-Hay So. 481-484 [doi]
• FPGA-accelerated retinal vessel-tree extractionAlejandro Nieto, Victor M. Brea, David López Vilariño. 485-488 [doi]
• Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithmDavid W. Thöni, Alfred Strey. 489-492 [doi]
• Dynamic Polymorphic Reconfiguration for anti-tamper circuitsR. Porter, S. J. Stone, Y.-C. Kim, J. T. McDonald, L. A. Starman. 493-497 [doi]
• Run-time Partial Reconfiguration speed investigation and architectural design space explorationMing Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch. 498-502 [doi]
• Dynamic reconfigurable mixed-signal architecture for safety critical applicationsRomuald Girardey, Michael Hübner, Jürgen Becker. 503-506 [doi]
• Using 3D integration technology to realize multi-context FPGAsAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne. 507-510 [doi]
• Mems optically reconfigurable gate arrayHironobu Morita, Minoru Watanabe. 511-515 [doi]
• Sharf: An FPGA-based customizable processor architectureCem Savas Bassoy, Henning Manteuffel, Friedrich Mayer-Lindenberg. 516-520 [doi]
• Multigigabit network traffic processingJiri Halak. 521-524 [doi]
• Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCsRohit Kumar, Ann Gordon-Ross. 525-529 [doi]
• Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable ProcessorsToru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano. 530-533 [doi]
• A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming modelSai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala. 534-538 [doi]
• Rapid design exploration framework for application-aware customization of soft core processorsAlok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan. 539-542 [doi]
• A novel states recovery technique for the TMR softcore processorShiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi. 543-546 [doi]
• Performance metrics for hybrid multi-tasking systemsKyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton. 547-550 [doi]
• Cooperative multithreading in dynamically reconfigurable systemsEnno Lübbers, Marco Platzner. 551-554 [doi]
• The educational processor Sweet-16Venelin Angelov, Volker Lindenstruth. 555-559 [doi]
• Secure FPGA technologies and techniquesAn Braeken, Serge Kubera, Frederik Trouillez, Abdellah Touhafi, Nele Mentens, Jo Vliegen. 560-563 [doi]
• FPGA supercomputing platforms: A surveyMariette Awad. 564-568 [doi]
• A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAsXabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Perez, Armando Astarloa. 569-573 [doi]
• Run-time resource management in fault-tolerant network on reconfigurable chipsMohammad Hosseinabady, José L. Núñez-Yáñez. 574-577 [doi]
• Hot-Swapping architecture extension for mitigation of permanent functional unit faultsZoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura. 578-581 [doi]
• SVM speaker verification system based on a low-cost FPGARafael Ramos-Lara, Mariano Lopez Garcia, Enrique F. Canto Navarro, Luis Puente-Rodriguez. 582-586 [doi]
• An FPGA-based embedded wideband audio codec systemChang Choo, Bhavya Bambhania, Woon Seob So, In Ki Hwang, Do Young Kim. 587-590 [doi]
• Off-line placement of hardware tasks on FPGAIkbel Belaid, Fabrice Muller, Benjemaa Maher. 591-595 [doi]
• Proteus: An architectural synthesis tool based on the stream programming paradigmNikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier, Abelardo López-Lagunas. 596-599 [doi]
• Binary Synthesis with multiple memory banks targeting array referencesYosi Ben-Asher, Nadav Rotem. 600-603 [doi]
• Mapping basic prefix computations to fast carry-chain structuresThomas B. Preußer, Rainer G. Spallek. 604-608 [doi]
• FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmeticRoberto Gutierrez, Javier Valls, Asuncion Perez-Pascual. 609-612 [doi]
• Compensating for variability in FPGAs by re-mapping and re-placementN. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung. 613-616 [doi]
• Synthesis of the SR programming language for complex FPGAsNick Gasson, Neil C. Audsley. 617-621 [doi]
• Exploiting synchronous placement for asynchronous circuits onto commercial FPGAsMaurizio Tranchero, Leonardo Maria Reyneri. 622-625 [doi]
• Using C-to-gates to program streaming image processing kernels efficiently on FPGAsKristof Denolf, Stephen Neuendorffer, Kees A. Vissers. 626-630 [doi]
• An FPGA based verification platform for HyperTransport 3.xHeiner Litz, Holger Fröning, Maximilian Thürmer, Ulrich Brüning. 631-634 [doi]
• A virus scanning engine using a parallel finite-input memory machine and MPUsHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura. 635-639 [doi]
• Tracking elephant flows in internet backbone traffic with an FPGA-based cacheMartin Zádník, Marco Canini, Andrew W. Moore, David J. Miller, Wei Li 0009. 640-644 [doi]
• A reconfigurable FIR/FFT unit for wireless telecommunication systemsMaroun Ojail, Raphaël David, Stéphane Chevobbe, Didier Demigny. 645-648 [doi]
• Efficient AES S-boxes implementation for non-volatile FPGAsLubos Gaspar, Milos Drutarovský, Viktor Fischer, Nathalie Bochard. 649-653 [doi]
• Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAsKenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 654-657 [doi]
• Compact FPGA implementation of CamelliaPanasayya Yalla, Jens-Peter Kaps. 658-661 [doi]
• FPGA-based acceleration of neural network for ranking in web search engine with a streaming architectureJing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-hsiung Hsu. 662-665 [doi]
• An FPGA design for evaluating score function in protein energy calculationJose Manuel Romero-Ximil, Arturo Diaz-Perez. 666-669 [doi]
• Emulating Spiking Neural Networks for edge detection on FPGA hardwareBrendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire, Qingxiang Wu. 670-673 [doi]
• A reconfigurable architecture for the Phylogenetic Likelihood FunctionNikolaos Alachiotis, Alexandros Stamatakis, Euripides Sotiriades, Apostolos Dollas. 674-678 [doi]
• Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulatorTomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano. 679-682 [doi]
• A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM)Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas. 683-686 [doi]
• Enhanced gradient-based motion vector coprocessorGuillermo Botella Juan, Antonio García Ríos, Uwe H. Meyer-Baese, Manuel Rodriguez, María C. Molina, Luís Parrilla Roure. 687-690 [doi]
• Dynamic reconfiguration system for real-time video processingSaya Hinaga, Yoshiki Yamaguchi, Tetsuhiko Yao, Tohru Kawabe. 691-694 [doi]
• Numerically controlled oscillators using linear approximationHans-Jörg Pfleiderer, Stefan Lachowicz. 695-698 [doi]
• Random numbers generation: Investigation of narrowtransitions suppression on FPGAVladimir Rozic, Ingrid Verbauwhede. 699-702 [doi]
• Improving the quality of a Physical Unclonable Function using configurable Ring OscillatorsAbhranil Maiti, Patrick Schaumont. 703-707 [doi]
• CREMA: A coarse-grain reconfigurable array with mapping adaptivenessFabio Garzia, Waqar Hussain, Jari Nurmi. 708-712 [doi]
• High-level programming of coarse-grained reconfigurable architecturesZain-ul-Abdin. 713-714 [doi]
• FPGA support for satellite computations of hyper spectral imagesCarlos González, Daniel Mozos, Javier Resano. 715-716 [doi]
• Improving the memory footprint and runtime scalability of FPGA CAD algorithmsScott Y. L. Chin, Steven J. E. Wilton. 717-718 [doi]
• Efficient techniques and methodologies for embedded system design usign free hardware and open standardsJ. I. Villar, J. Juan, Manuel J. Bellido. 719-720 [doi]
• Multi-terminal BDD synthesis and applicationsPetr Mikusek. 721-722 [doi]
• Soft errors in Flash-based FPGAs: Analysis methodologies and first resultsNiccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante. 723-724 [doi]
• RISPP: A run-time adaptive reconfigurable embedded processorLars Bauer, Muhammad Shafique, Jörg Henkel. 725-726 [doi]