Abstract is missing.
- An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIsY. Takei, A. Onozawat, K. Kawaitt, H. Kitazawa. 2-7 [doi]
- A Full-Swing Bootstrapped BiCMOS BufferElizabeth J. Brauer, Pradeep Elamanchili. 8-13 [doi]
- A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systemsJoão Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije. 14 [doi]
- On Generating Test Sets that Remain Valid in the Presence of Undetected FaultsIrith Pomeranz, Sudhakar M. Reddy. 20-25 [doi]
- A New Heuristic Algorithm for Estimating Signal and Detection ProbabilitiesMusaed A. Al-Kharji, Sami A. Al-Arian. 26-31 [doi]
- Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational NetworksCristiana Bolchini, Fabio Salice, Donatella Sciuto. 32 [doi]
- Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric VariablesHiroshi Sawada, Shigeru Yamashita, Akira Nagoya. 39-44 [doi]
- A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital CircuitsAndreas G. Veneris, Ibrahim N. Hajj. 45-50 [doi]
- OLIVIA: Objectoriented Logicsimulation Implementing the VITAL StandardJosef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich. 51 [doi]
- Hardware interface design for real time embedded systemsAdel Baganne, Jean Luc Philippe, Eric Martin. 58-63 [doi]
- A System Design Methodology for Telecommunication Network ApplicationsJulio Leao da Silva Jr., Chantal Ykman-Couvreur, Bill Lin, Hugo De Man, Gjalt G. de Jong. 64-69 [doi]
- Accurate Entropy Calculation for Large Logic Circuits Based on Output ClusteringAntonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello. 70 [doi]
- Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based SystemsLuca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano. 77-82 [doi]
- Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective PrechargeShaoyi Wang. 83-85 [doi]
- A New Low-Voltage Full Adder CircuitHanho Lee, Gerald E. Sobelman. 88 [doi]
- VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip SupportFabio Ancona, Giorgio Oddone, Stefano Rovetta, Gianni Uneddu, Rodolfo Zunino. 94-99 [doi]
- A new method for asynchronous pipeline controlSam S. Appleton, Shannon V. Morton, Michael J. Liebelt. 100-104 [doi]
- The MGAP Family of Processor ArraysKevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin. 105 [doi]
- An Efficient Dynamic Parallel Approach to Automatic Test Pattern GenerationH.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus. 112-117 [doi]
- Use of Statecharts-Related Description to Achieve Testable Design of Control SubsystemsFranco Fummi, Mariagiovanna Sami, F. Tartarini. 118-123 [doi]
- How an Evolving Fault Model Improves the Behavioral Test GenerationGiacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto. 124 [doi]
- A prototype chipset for a large scaleable ATM switching nodeMichael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi. 131-136 [doi]
- Analog Circuit Model of Lamprey Unit Pattern GeneratorElizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas. 137-142 [doi]
- A New CMOS Tunable Transconductor Dedicated to VHF Continuous-Time FiltersAli Assi, Mohamad Sawan, Rabin Raut. 143 [doi]
- Scheduling with Confidence for Probabilistic Data-flow GraphsSissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos. 150-155 [doi]
- A low power based system partitioning and binding technique for multi-chip module architecturesRaghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy. 156-162 [doi]
- Algorithm and Hardware Support for Branch AnticipationTed Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju. 163 [doi]
- Modular Design of Communication Node PrototypesSergio D Angelo, Lauro Mantoani, Riccardo P. G. Mazzei, Stefania Russo, Giacomo R. Sechi. 170-175 [doi]
- Parallel VLSI Architectures for Cryptographic SystemsFabio Ancona, Alessandro De Gloria, Rodolfo Zunino. 176-181 [doi]
- A Clocked, Static Circuit Technique for Building Efficient High Frequency PipelinesEric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin. 182 [doi]