Abstract is missing.
- Why Is It So Hard to Make Secure Chips?Marc Witteman. 1 [doi]
- Design and Implementation of Real-Time Multi-sensor Vision SystemsYusuf Leblebici. 3 [doi]
- Medical Device Security: The First 165 YearsKevin Fu. 5 [doi]
- VLSI Design Methods for Low Power Embedded EncryptionIngrid Verbauwhede. 7 [doi]
- High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key CryptosystemsChaohui Du, Guoqiang Bai, Xingjun Wu. 9-14 [doi]
- Reduced Overhead Gate Level Logic EncryptionKyle Juretus, Ioannis Savidis. 15-20 [doi]
- A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register FileSalin Junsangsri, Jie Han, Fabrizio Lombardi. 21-26 [doi]
- A Clockless Sequential PUF with Autonomous Majority VotingXiaolin Xu, Daniel E. Holcomb. 27-32 [doi]
- Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic ComputingBo Yuan, Yanzhi Wang, Zhongfeng Wang. 33-38 [doi]
- Concurrent Error Detection for Reliable SHA-3 DesignPei Luo, Cheng Li, Yunsi Fei. 39-44 [doi]
- Secure Model Checkers for Network-on-Chip (NoC) ArchitecturesTravis Boraten, Dominic DiTomaso, Avinash Karanth Kodi. 45-50 [doi]
- Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield OptimizationSita kondamadugula, Srinath R. Naidu. 51-56 [doi]
- Low Energy Sketching Engines on Many-Core Platform for Big Data AccelerationAmey M. Kulkarni, Tahmid Abtahi, Emily Smith, Tinoosh Mohsenin. 57-62 [doi]
- Low-Power Manycore Accelerator for Personalized Biomedical ApplicationsAdam Page, Nasrin Attaran, Colin Shea, Houman Homayoun, Tinoosh Mohsenin. 63-68 [doi]
- Hardware Security Threats and Potential Countermeasures in Emerging 3D ICsJaya Dofe, Qiaoyan Yu, Hailang Wang, Emre Salman. 69-74 [doi]
- Real-Time Analysis for Wormhole NoC: Revisited and RevisedQin Xiong, Zhonghai Lu, Fei Wu, Changsheng Xie. 75-80 [doi]
- A New Methodology for Noise Sensor Placement Based on Association Rule MiningYu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin, Chia-Hsin Lee. 81-86 [doi]
- MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed RouterXiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu. 87-92 [doi]
- Modular Placement for Interposer based Multi-FPGA SystemsFubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma. 93-98 [doi]
- A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen DesignZhezhao Xu, Wenjian Yu, Chao Zhang, Bolong Zhang, Meijuan Lu, Michael Mascagni. 99-104 [doi]
- Real-Time Hardware Stereo Matching Using Guided Image FilterChen Yang, Yan Li, Wei Zhong, Song Chen. 105-108 [doi]
- Computing Complex Functions using Factorization in Unipolar Stochastic LogicYin Liu, Keshab K. Parhi. 109-112 [doi]
- DCC: Double Capacity Cache Architecture for Narrow-Width ValuesMohsen Imani, Shruti Patil, Tajana S. Rosing. 113-116 [doi]
- Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery TechniquesNidhi Batra, Pawan Sehgal, Shashwat Kaushik, Mohammad S. Hashmi, Sudesh Bhalla, Anuj Grover. 117-120 [doi]
- Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event DetectionAditya Dalakoti, Carrie Segal, Merritt Miller, Forrest Brewer. 121-124 [doi]
- Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural LevelWei Wei, Kazuteru Namba, Fabrizio Lombardi. 125-128 [doi]
- A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCsDaniel Prashanth, Hae-Seung Lee. 129-132 [doi]
- Secure and Low-Overhead Circuit Obfuscation Technique with MultiplexersXueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu. 133-136 [doi]
- Task-Resource Co-Allocation for Hotspot Minimization in Heterogeneous Many-Core NoCsMd Farhadur Reza, Dan Zhao, Hongyi Wu. 137-140 [doi]
- Guiding Power/Quality Exploration for Communication-Intense Stream ProcessingHamed Tabkhi, Majid Sabbagh, Gunar Schirner. 141-144 [doi]
- Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array ArchitectureValerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino. 145-150 [doi]
- A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation ToleranceGovinda Sannena, Bishnu Prasad Das. 151-156 [doi]
- Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded SystemsTosiron Adegbija. 157-162 [doi]
- Multiple Attempt Write Strategy for Low Energy STT-RAMJaeyoung Park, Michael Orshansky. 163-168 [doi]
- Secret Sharing and Multi-user Authentication: From Visual Cryptography to RRAM CircuitsMd Tanvir Arafin, Gang Qu. 169-174 [doi]
- Defense Systems and IoT: Security Issues in an Era of Distributed Command and ControlDoug Palmer, Saverio Fazzari, Scott Wartenberg. 175-179 [doi]
- Security Meets Nanoelectronics for Internet of Things ApplicationsGarrett S. Rose. 181-183 [doi]
- Tracking Data Flow at Gate-Level through Structural CheckingThao Le, Jia Di, Mark Tehranipoor, Domenic Forte, Lei Wang 0003. 185-189 [doi]
- Design of Error-Resilient Logic Gates with Reinforcement Using ImplicationsXijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson. 191-196 [doi]
- Reducing Soft-error Vulnerability of Caches using Data CompressionSparsh Mittal, Jeffrey S. Vetter. 197-202 [doi]
- Workload-Aware Worst Path Analysis of Processor-Scale NBTI DegradationSong Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato. 203-208 [doi]
- Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault PropagationRalph Nyberg, Johann Heyszl, Dietmar Heinz, Georg Sigl. 209-214 [doi]
- A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoCYongsuk Choi, Yong-Bin Kim. 215-219 [doi]
- A General Sign Bit Error Correction Scheme for Approximate AddersRui Zhou, Weikang Qian. 221-226 [doi]
- 2/Hf 1T1R RRAM Memory CellAmr M. S. Tosson, Mohab Anis, Lan Wei. 227-232 [doi]
- Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICsRavi Patel, Kan Xu, Eby G. Friedman, Praveen Raghavan. 233-238 [doi]
- 8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM DesignAmr M. S. Tosson Abdelwahed, Adam Neale, Mohab Anis, Lan Wei. 239-244 [doi]
- Polynomial Arithmetic Using Sequential Stochastic LogicNaman Saraf, Kia Bazargan. 245-250 [doi]
- Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall DevicesYu Bai, Bo Hu, Weidong Kuang, Mingjie Lin. 251-256 [doi]
- Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled InterconnectsIoannis A. Papistas, Vasilis F. Pavlidis. 257-262 [doi]
- Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing TreesSubrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das. 263-268 [doi]
- VarDroid: Online Variability Emulation in Android/Linux PlatformsPietro Mercati, Francesco Paterna, Andrea Bartolini, Mohsen Imani, Luca Benini, Tajana Simunic Rosing. 269-274 [doi]
- Neural Network-based Prediction Algorithms for In-Door Multi-Source Energy Harvesting System for Non-Volatile ProcessorsNing Liu, Caiwen Ding, Yanzhi Wang, Jingtong Hu. 275-280 [doi]
- A Unified Model of Power Sources for the Simulation of Electrical Energy SystemsSara Vinco, Yukai Chen, Enrico Macii, Massimo Poncino. 281-286 [doi]
- Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC DesignsMunish Jassi, Uzair Sharif, Daniel Müller-Gritschneder, Ulf Schlichtmann. 287-292 [doi]
- Extracting Designs of Secure IPs Using FPGA CAD ToolsVincent Mirian, Paul Chow. 293-298 [doi]
- Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAMRobert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia. 299-304 [doi]
- Enhancing Hardware Security with Emerging Transistor TechnologiesYu Bi, Xiaobo Sharon Hu, Yier Jin, Michael T. Niemier, Kaveh Shamsi, Xunzhao Yin. 305-310 [doi]
- The Applications of NVM Technology in Hardware SecurityChaofei Yang, Beiye Liu, Yandan Wang, Yiran Chen, Hai Li, Xian Zhang, Guangyu Sun. 311-316 [doi]
- Survey of Emerging Technology Based Physical Unclonable FuntionsIlia A. Bautista Adames, Jayita Das, Sanjukta Bhanja. 317-322 [doi]
- Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCsYong Chen, Emil Matús, Gerhard P. Fettweis. 323-328 [doi]
- Prolonging Lifetime of Non-volatile Last Level Caches with Cluster MappingMorteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi. 329-334 [doi]
- A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-ProcessorsAnastasios Psarras, JungHee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 335-340 [doi]
- Dynamic Real-Time Scheduler for Large-Scale MPSoCsMarcelo Ruaro, Fernando Gehm Moraes. 341-346 [doi]
- Leveraging 3D Technologies for Hardware Security: Opportunities and ChallengesPeng Gu, Shuangchen Li, Dylan Stow, Russell Barnes, Liu Liu, Yuan Xie 0001, Eren Kursun. 347-352 [doi]
- FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile GamesJiachen Song, Xi Li, Beilei Sun, Zhinan Cheng, Chao Wang, Xuehai Zhou. 353-356 [doi]
- Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded DevicesMohamad Hammam Alsafrjalani, Ann Gordon-Ross. 357-360 [doi]
- Temperature-aware Dynamic Voltage Scaling for Near-Threshold ComputingSaman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 361-364 [doi]
- Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent PathsTuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal, Sanjay Tanaji Shinde, Jacob Mathews, Rekha K. James. 365-368 [doi]
- An Enhanced Analytical Electrical Masking Model for Multiple Event TransientsAdam Watkins, Spyros Tragoudas. 369-372 [doi]
- Capturing True Workload Dependency of BTI-induced Degradation in CPU ComponentsDimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic. 373-376 [doi]
- Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore SystemsVijeta Rathore, Vivek Chaturvedi, Thambipillai Srikanthan. 377-380 [doi]
- ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation SystemJordi Perez-Puigdemont, Francesc Moll. 381-384 [doi]
- Red-Shield: Shielding Read Disturbance for STT-RAM Based Register Files on GPUsHang Zhang, Xuhao Chen, Nong Xiao, Fang Liu, Zhiguang Chen. 389-392 [doi]
- Modeling and Study of Two-BDT-Nanostructure based Sequential Logic CircuitsPoorna Marthi, Sheikh Rufsan Reza, Nazir Hossain, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González. 393-396 [doi]
- Exploring Main Memory Design Based on Racetrack Memory TechnologyQingda Hu, Guangyu Sun, Jiwu Shu, Chao Zhang. 397-402 [doi]
- An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile MemoriesAli Alsuwaiyan, Kartik Mohanram. 403-408 [doi]
- Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic DevicesRajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori. 409-414 [doi]
- Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist CircuitryHassan Afzali-Kusha, Alireza Shafaei, Massoud Pedram. 415-420 [doi]
- Approximate Differential Encoding for Energy-Efficient Serial CommunicationDaniele Jahier Pagliari, Enrico Macii, Massimo Poncino. 421-426 [doi]
- Fast Thermal Simulation using SystemC-AMSYukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino. 427-432 [doi]
- Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal AcquisitionCosimo Aprile, Luca Baldassarre, Vipul Gupta, Juhwan Yoo, Mahsa Shoaran, Yusuf Leblebici, Volkan Cevher. 433-438 [doi]
- Load Balanced On-Chip Power Delivery for Average Current DemandDivya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis. 439-444 [doi]