Abstract is missing.
- The Software Industry: Ten Lessons for Long LifeTimothy Chou. 3 [doi]
- Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage VariationEd Grochowski, David Ayers, Vivek Tiwari. 7-16 [doi]
- Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal ManagementKevin Skadron, Tarek F. Abdelzaher, Mircea R. Stan. 17-28 [doi]
- Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency ScalingGreg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott. 29-42 [doi]
- Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for MultiprocessorsMarcelo H. Cintra, Josep Torrellas. 43-54 [doi]
- Thread-Spawning Schemes for Speculative MultithreadingPedro Marcuello, Antonio González. 55-64 [doi]
- Reverse Tracer: A Software Tool for Generating Realistic Performance Test ProgramsMariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, Yasunori Kimura. 81-91 [doi]
- Tuning Garbage Collection in an Embedded Java EnvironmentGuangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko. 92 [doi]
- Fine-Grain Priority Scheduling on Multi-Channel Memory SystemsZhichun Zhu, Zhao Zhang, Xiaodong Zhang. 107-116 [doi]
- The Minimax Cache: An Energy-Efficient Framework for Media ProcessorsOsman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz. 131-140 [doi]
- Using Complete Machine Simulation for Software Power Estimation: The SoftWatt ApproachSudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John. 141-150 [doi]
- Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-DelaySe-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar. 151 [doi]
- Let s Study Whole-Program Cache Behaviour AnalyticallyXavier Vera, Jingling Xue. 175-186 [doi]
- Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative PrecomputationPerry H. Wang, Hong Wang 0003, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen. 187-196 [doi]
- Quantifying Load Stream BehaviorSuleyman Sair, Timothy Sherwood, Brad Calder. 197 [doi]
- Modeling Value SpeculationYiannakis Sazeides. 211-222 [doi]
- The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional BranchesMartin Kämpe, Per Stenström, Michel Dubois. 223-232 [doi]
- Power Issues Related to Branch PredictionDharmesh Parikh, Kevin Skadron, Yan Zhang, Marco Barcella, Mircea R. Stan. 233 [doi]
- Recovery Oriented Computing: A New Research Agenda for a New CenturyDavid A. Patterson. 247 [doi]
- Bandwidth Adaptive SnoopingMilo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood. 251-262 [doi]
- CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory ClustersPeter Jamieson, Angelos Bilas. 263-274 [doi]
- User-Level Communication in Cluster-Based ServersEnrique V. Carrera, Srinath Rao, Liviu Iftode, Ricardo Bianchini. 275 [doi]
- Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register FilesMary D. Brown, Yale N. Patt. 289-298 [doi]
- Loose Loops Sink ChipsEric Borch, Eric Tune, Srilatha Manne, Joel S. Emer. 299-310 [doi]
- Evaluation of a Multithreaded Architecture for Cellular ComputingCalin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.. 311-322 [doi]