Abstract is missing.
- New architectures for a new biologyDoug E. Shaw. 4 [doi]
- BulletProof: a defect-tolerant CMP switch architectureKypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky. 5-16 [doi]
- CMP design space exploration subject to physical constraintsYingmin Li, Benjamin Lee, David Brooks, Zhigang Hu, Kevin Skadron. 17-28 [doi]
- Exploiting parallelism and structure to accelerate the simulation of chip multi-processorsDavid A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors. 29-40 [doi]
- An approach for implementing efficient superscalar CISC processorsShiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith. 41-52 [doi]
- A decoupled KILO-instruction processorMiquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero. 53-64 [doi]
- Store vectors for scalable memory dependence prediction and schedulingSamantika Subramaniam, Gabriel H. Loh. 65-76 [doi]
- Dynamic power-performance adaptation of parallel computation on chip multiprocessorsJian Li, José F. Martínez. 77-87 [doi]
- Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloadsAamer Jaleel, Matthew Mattina, Bruce L. Jacob. 88-98 [doi]
- Construction and use of linear regression models for processor performance analysisP. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil. 99-108 [doi]
- Chip-multiprocessing and beyondPer Stenström. 109 [doi]
- Probabilistic counter updates for predictor hysteresis and stratificationNicholas Riley, Craig B. Zilles. 110-120 [doi]
- Phase characterization for power: evaluating control-flow-based and event-counter-based techniquesCanturk Isci, Margaret Martonosi. 121-132 [doi]
- DMA-aware memory energy managementVivek Pandey, Weihang Jiang, Yuanyuan Zhou, Ricardo Bianchini. 133-144 [doi]
- Increasing the cache efficiency by eliminating noisePrateek Pujara, Aneesh Aggarwal. 145-154 [doi]
- Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAMRavi K. Venkatesan, Stephen Herr, Eric Rotenberg. 155-165 [doi]
- Completely verifying memory consistency of test program executionsChaiyasit Manovit, Sudheendra Hangal. 166-175 [doi]
- Understanding the performance-temperature interactions in disk I/O of server workloadsYoungjae Kim, Sudhanva Gurumurthi, Anand Sivasubramaniam. 176-186 [doi]
- High performance file I/O for the Blue Gene/L supercomputerHao Yu, Ramendra K. Sahoo, C. Howson, G. Almasi, José G. Castaños, M. Gupta, José E. Moreira, J. J. Parker, Thomas Engelsiepen, Robert B. Ross, Rajeev Thakur, Robert Latham, William D. Gropp. 187-196 [doi]
- ReViveI/O: efficient handling of I/O in highly-available rollback-recovery serversJun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas. 200-211 [doi]
- Industrial Perspectives: System IO Network Evolution - Closing Requirement GapsRenato Recio. 201-201 [doi]
- Industrial Perspectives: Platform Design Challenges with Many coresRaj Yavatkar. 201-201 [doi]
- Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip BandwidthPhilip G. Emma. 201-201 [doi]
- Reducing resource redundancy for concurrent error detection techniques in high performance microprocessorsSumeet Kumar, Aneesh Aggarwal. 212-221 [doi]
- InfoShield: a security architecture for protecting information usage in memoryWeidong Shi, Joshua B. Fryman, Guofei Gu, Hsien-Hsin S. Lee, Youtao Zhang, Jun Yang. 222-231 [doi]
- CORD: cost-effective (and nearly overhead-free) order-recording and data race detectionMilos Prvulovic. 232-243 [doi]
- Software-hardware cooperative memory disambiguationRuke Huang, Alok Garg, Michael C. Huang. 244-253 [doi]
- LogTM: log-based transactional memoryKevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, David A. Wood. 254-265 [doi]
- The common case transactional behavior of multithreaded programsJaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun. 266-277 [doi]
- Speculative synchronization and thread management for fine granularity threadsAlex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover. 278-287 [doi]
- Efficient instruction schedulers for SMT processorsJoseph J. Sharkey, Dmitry V. Ponomarev. 288-298 [doi]