Abstract is missing.
- Interconnect-Centric ComputingWilliam J. Dally. 1 [doi]
- An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip MultiprocessorsHaakon Dybdahl, Per Stenström. 2-12 [doi]
- Evaluating MapReduce for Multi-core and Multiprocessor SystemsColby Ranger, Ramanan Raghuraman, Arun Penmetsa, Gary R. Bradski, Christos Kozyrakis. 13-24 [doi]
- Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread ApplicationsHongtao Zhong, Steven A. Lieberman, Scott A. Mahlke. 25-36 [doi]
- Implications of Device Timing Variability on Full Chip TimingMurali Annavaram, Ed Grochowski, Paul Reed. 37-45 [doi]
- Optical Interconnect Opportunities for Future Server Memory SystemsY. Katayama, A. Okazaki. 46-50 [doi]
- Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware PrefetchersSanthosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt. 63-74 [doi]
- Improving Branch Prediction and Predicated Execution in Out-of-Order ProcessorsEduardo Quiñones, Joan-Manuel Parcerisa, Antonio González. 75-84 [doi]
- Accelerating and Adapting Precomputation Threads for Effcient PrefetchingWeifeng Zhang, Dean M. Tullsen, Brad Calder. 85-95 [doi]
- Petascale Computing Research Challenges - A Manycore PerspectiveSteve Pawlowski. 96 [doi]
- A Scalable, Non-blocking Approach to Transactional MemoryHassan Chafi, Jared Casper, Brian D. Carlstrom, Austen McDonald, Chi Cao Minh, Woongki Baek, Christos Kozyrakis, Kunle Olukotun. 97-108 [doi]
- Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and ScalingBrinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob. 109-120 [doi]
- HARD: Hardware-Assisted Lockset-based Race DetectionPin Zhou, Radu Teodorescu, Yuanyuan Zhou. 121-132 [doi]
- Colorama: Architectural Support for Data-Centric SynchronizationLuis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas. 133-144 [doi]
- Error Detection via Online Checking of Cache Coherence with Token Coherence SignaturesAlbert Meixner, Daniel J. Sorin. 145-156 [doi]
- A Low Overhead Fault Tolerant Coherence Protocol for CMP ArchitecturesRicardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato. 157-168 [doi]
- Perturbation-based Fault ScreeningPaul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee. 169-180 [doi]
- Application-Level Correctness and its Impact on Fault ToleranceXuanhua Li, Donald Yeung. 181-192 [doi]
- Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated ProcessorsKiran Puttaswamy, Gabriel H. Loh. 193-204 [doi]
- Modeling and Managing Thermal Profiles of Rack-mounted Servers with ThermoStatJeonghwan Choi, Youngjae Kim, Anand Sivasubramaniam, Jelena Srebric, Qian Wang, Joonwon Lee. 205-215 [doi]
- Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic MappingNathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner. 216-227 [doi]
- Interactions Between Compression and Prefetching in Chip MultiprocessorsAlaa R. Alameldeen, David A. Wood. 228-239 [doi]
- A Memory-Level Parallelism Aware Fetch Policy for SMT ProcessorsStijn Eyerman, Lieven Eeckhout. 240-249 [doi]
- Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache LinesMoinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt. 250-259 [doi]
- LogTM-SE: Decoupling Hardware Transactional Memory from CachesLuke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, David A. Wood. 261-272 [doi]
- MemTracker: Efficient and Programmable Support for Memory Access Monitoring and DebuggingGuru Venkataramani, Brandyn Roemer, Yan Solihin, Milos Prvulovic. 273-284 [doi]
- A Burst Scheduling Access Reordering MechanismJun Shao, Brian T. Davis. 285-294 [doi]
- Exploiting Postdominance for Speculative ParallelizationMayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone, Matthew I. Frank. 295-305 [doi]
- Concurrent Direct Network Access for Virtual Machine MonitorsJeffrey Shafer, David Carr, Aravind Menon, Scott Rixner, Alan L. Cox, Willy Zwaenepoel, Paul Willmann. 306-317 [doi]
- A Domain-Specific On-Chip Network Design for Large Scale Cache SystemsYuho Jin, Eun Jung Kim, Ki Hwan Yum. 318-327 [doi]
- An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer SharingLiqun Cheng, John B. Carter, Donglai Dai. 328-339 [doi]
- Illustrative Design Space Studies with Microarchitectural Regression ModelsBenjamin C. Lee, David M. Brooks. 340-351 [doi]