Table of Contents

• Programming the cloudJames R. Larus. 1 [doi]
• Achieving uniform performance and maximizing throughput in the presence of heterogeneityKrishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David Brooks. 3-14 [doi]
• Fg-STP: Fine-Grain Single Thread Partitioning on MulticoresRakesh Ranjan, Fernando Latorre, Pedro Marcuello, Antonio González. 15-24 [doi]
• Thread block compaction for efficient SIMT control flowWilson W. L. Fung, Tor M. Aamodt. 25-36 [doi]
• Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processorsHamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim. 38-49 [doi]
• Relaxing non-volatility for fast and energy-efficient STT-RAM cachesClinton Wills Smullen IV, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan. 50-61 [doi]
• Shared last-level TLBs for chip multiprocessorsAbhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi. 62-63 [doi]
• Bloom Filter Guided Transaction SchedulingGeoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge. 75-86 [doi]
• Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanismMojtaba Mehrara, Po-Chun Hsu, Mehrzad Samadi, Scott A. Mahlke. 87-98 [doi]
• HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessorSanghoon Lee 0006, Devesh Tiwari, Yan Solihin, James Tuck. 99-110 [doi]
• MOPED: Orchestrating interprocess message data on CMPsJunli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun. 111-120 [doi]
• Addressing system-level trimming issues in on-chip nanophotonic networksChristopher Nitta, Matthew K. Farrens, Venkatesh Akella. 122-131 [doi]
• Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocolsDana Vantrease, Mikko H. Lipasti, Nathan L. Binkert. 132-143 [doi]
• CHIPPER: A low-complexity bufferless deflection routerChris Fallin, Chris Craik, Onur Mutlu. 144-155 [doi]
• Power shifting in Thrifty Interconnection NetworkJian Li, Wei Huang, Charles Lefurgy, Lixin Zhang 0002, Wolfgang E. Denzel, Richard R. Treumann, Kun Wang. 156-167 [doi]
• Cuckoo directory: A scalable directory for many-core systemsMichael Ferdman, Pejman Lotfi-Kamran, Ken Balet, Babak Falsafi. 169-180 [doi]
• Data-triggered threads: Eliminating redundant computationHung-Wei Tseng, Dean M. Tullsen. 181-192 [doi]
• Fast thread migration via cache working set predictionJeffery A. Brown, Leo Porter, Dean M. Tullsen. 193-204 [doi]
• SolarCore: Solar energy driven multi-core architecture power managementChao Li, Wangyuan Zhang, Chang-Burm Cho, Tao Li. 205-216 [doi]
• How s the parallel computing revolution going?Kathryn S. McKinley. 217 [doi]
• CloudCache: Expanding and shrinking private cachesHyunjin Lee, Sangyeun Cho, Bruce R. Childers. 219-230 [doi]
• MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchyShekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie. 231-242 [doi]
• NUcache: An efficient multicore cache organization based on Next-Use distanceR. Manikantan, Kaushik Rajan, R. Govindarajan. 243-253 [doi]
• A new server I/O architecture for high speed networksGuangdeng Liao, Xia Znu, Laxmi N. Bhuyan. 255-265 [doi]
• Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processingFeng Chen, Rubao Lee, Xiaodong Zhang. 266-277 [doi]
• I-CASH: Intelligently Coupled Array of SSD and HDDQing Yang, Jin Ren. 278-289 [doi]
• A case for guarded power gating for multi-core processorsNiti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram. 291-300 [doi]
• Beyond block I/O: Rethinking traditional storage primitivesXiangyong Ouyang, David W. Nellans, Robert Wipfel, David Flynn, Dhabaleswar K. Panda. 301-311 [doi]
• Efficient data streaming with on-chip accelerators: Opportunities and challengesRui Hou, Lixin Zhang, Michael C. Huang, Kun Wang, Hubertus Franke, Yi Ge, Xiaotao Chang. 312-320 [doi]
• Hardware/software-based diagnosis of load-store queues using expandable activity logsJavier Carretero, Xavier Vera, Jaume Abella, Tanausu Ramirez, Matteo Monchiero, Antonio González. 321-331 [doi]
• Calvin: Deterministic or not? Free will to chooseDerek Hower, Polina Dudnik, Mark D. Hill, David A. Wood. 333-334 [doi]
• Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory systemMadhura Joshi, Wangyuan Zhang, Tao Li. 345-356 [doi]
• Offline symbolic analysis to infer Total Store OrderDongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang. 357-358 [doi]
• Safe and efficient supervised memory systemsJayaram Bobba, Marc Lupon, Mark D. Hill, David A. Wood. 369-380 [doi]
• A quantitative performance analysis model for GPU architecturesYao Zhang, John D. Owens. 382-393 [doi]
• Abstraction and microarchitecture scaling in early-stage power modelingHans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer. 394-405 [doi]
• HAsim: FPGA-based high-detail multicore simulation using time-division multiplexingMichael Pellauer, Michael Adler, Michel Kinsy, Angshuman Parashar, Joel S. Emer. 406-417 [doi]
• Checked Load: Architectural support for JavaScript type-checking on mobile processorsOwen Anderson, Emily Fortuna, Luis Ceze, Susan Eggers. 419-430 [doi]
• Exploiting criticality to reduce bottlenecks in distributed uniprocessorsBehnam Robatmili, Madhu Saravana Sibi Govindan, Doug Burger, Stephen W. Keckler. 431-442 [doi]
• Storage free confidence estimation for the TAGE branch predictorAndré Seznec. 443-454 [doi]
• Architectural framework for supporting operating system survivabilityXiaowei Jiang, Yan Solihin. 456-465 [doi]
• FREE-p: Protecting non-volatile memory against both hard and soft errorsDoe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez. 466-477 [doi]
• Practical and secure PCM systems by online detection of malicious write streamsMoinuddin K. Qureshi, André Seznec, Luis Lastras, Michele Franceschini. 478-489 [doi]
• Efficient complex operators for irregular codesJack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor. 491-502 [doi]
• Dynamically Specialized Datapaths for energy efficient computingVenkatraman Govindaraju, Chen-Han Ho, Karthikeyan Sankaralingam. 503-514 [doi]
• Hardware/software techniques for DRAM thermal managementSong Liu, Brian Leung, Alexander Neckar, Seda Ogrenci Memik, Gokhan Memik, Nikos Hardavellas. 515-525 [doi]
• ACCESS: Smart scheduling for asymmetric cache CMPsXiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das. 527-538 [doi]
• Archipelago: A polymorphic cache design for enabling robust near-threshold operationAmin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke. 539-550 [doi]