Table of Contents

• New methods for parallel pattern fast fault simulation for synchronous sequential circuitsMehrdad Mojtahedi, Walter Geisselhardt. 2-5 [doi]
• Fault behavior dictionary for simulation of device-level transientsGwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab. 6-9 [doi]
• New methods of improving parallel fault simulation in synchronous sequential circuitsHyung Ki Lee, Dong Sam Ha. 10-17 [doi]
• Exploiting hardware sharing in high-level synthesis for partial scan optimizationSujit Dey, Miodrag Potkonjak, Rabindra K. Roy. 20-25 [doi]
• High level synthesis for reconfigurable datapath structuresLisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey. 26-29 [doi]
• An improved method for RTL synthesis with testability tradeoffsHaidar Harmanani, Christos A. Papachristou. 30-35 [doi]
• Interleaving based variable ordering methods for ordered binary decision diagramsHiroshige Fujii, Goichi Ootomo, Chikahiro Hori. 38-41 [doi]
• Dynamic variable ordering for ordered binary decision diagramsRichard Rudell. 42-47 [doi]
• Breadth-first manipulation of very large binary-decision diagramsHiroyuki Ochi, Koichi Yasuoka, Shuzo Yajima. 48-55 [doi]
• An efficient methodology for extraction and simulation of transmission lines for application specific electronic modulesS. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, T. Savarino, Dean P. Neikirk, Lawrence T. Pillage. 58-65 [doi]
• Simulating 3-D retarded interconnect models using complex frequency hopping (CFH)Eli Chiprout, Hansruedi Heeb, Michel S. Nakhla, Albert E. Ruehli. 66-72 [doi]
• Bounds on net lengths for high-speed PCBJaebum Lee, Eugene Shragowitz, David J. Poli. 73-76 [doi]
• A net-oriented method for realistic fault analysisHua Xue, Chennian Di, Jochen A. G. Jess. 78-83 [doi]
• On-chip test generation for combinational circuits by LFSR modificationShambhu J. Upadhyaya, Liang-Chi Chen. 84-87 [doi]
• Fault-based automatic test generator for linear analog circuitsNaveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham. 88-91 [doi]
• A grid-based approach for connectivity binding with geometric costsHyuk-Jae Jang, Barry M. Pangrle. 94-99 [doi]
• Layout-driven module selection for register-transfer synthesis of sub-micron ASIC sVasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru. 100-103 [doi]
• Design tool integration using object-oriented database viewsElke A. Rundensteiner. 104-107 [doi]
• Beyond the combinatorial limit in depth minimization for LUT-based FPGA designsJason Cong, Yuzheng Ding. 110-114 [doi]
• Cube-packing and two-level minimizationRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 115-122 [doi]
• Combining technology mapping and placement for delay-optimization in FPGA designsChau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin. 123-127 [doi]
• Parallel timing simulation on a distributed memory multiprocessorChih-Po Wen, Katherine A. Yelick. 130-135 [doi]
• Event driven adaptively controlled explicit simulation of integrated circuitsAnirudh Devgan, Ronald A. Rohrer. 136-140 [doi]
• Simulating sigma-delta modulators in AWEswitRichard J. Trihy, Ronald A. Rohrer. 141-144 [doi]
• Practical applications of an efficient time separation of events algorithmHenrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello. 146-151 [doi]
• Min-max linear programming and the timing analysis of digital circuitsTimothy M. Burks, Karem A. Sakallah. 152-155 [doi]
• Minimum padding to satisfy short path constraintsNarendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 156-161 [doi]
• A combined hierarchical placement algorithmHyunchul Shin, Chunghee Kim, Wonjong Kim, Myoungsub Oh, Kwangjoon Rhee, Seogyun Choi, Heasoo Chung. 164-169 [doi]
• Efficient and effective placement for very large circuitsWern-Jieh Sun, Carl Sechen. 170-177 [doi]
• SEFOP: a novel approach to data path module placementChih-Liang Eric Cheng, Ching-yen Ho. 178-181 [doi]
• Computing the observable equivalence relation of a finite state machineThomas Tamisier. 184-187 [doi]
• Algebraic decision diagrams and their applicationsR. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi. 188-191 [doi]
• Representation and symbolic manipulation of linearly inductive Boolean functionsAarti Gupta, Allan L. Fisher. 192-199 [doi]
• Test quality and yield analysis using the DEFAM defect to fault mapperDinesh D. Gaitonde, Duncan M. Hank Walker. 202-205 [doi]
• Convexity-based algorithms for design centeringSachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang. 206-209 [doi]
• Style: a technology-independent approach to statistical designJulie Chen, Andrew T. Yang. 210-214 [doi]
• Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuitsKerry S. Lowe, P. Glenn Gulak. 216-219 [doi]
• A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit areaWeitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj. 220-223 [doi]
• Efficient estimation of dynamic power consumption under a real delay modelChi-Ying Tsui, Massoud Pedram, Alvin M. Despain. 224-228 [doi]
• Architecture and routability analysis for row-based FPGAsMassoud Pedram, Bahman S. Nobandegani, Bryan Preas. 230-235 [doi]
• Partitioning with cone structuresGabriele Saucier, Daniel R. Brasen, J. P. Hiol. 236-239 [doi]
• Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphsEnric Pastor, Jordi Cortadella. 250-254 [doi]
• Unifying synchronous/asynchronous state machine synthesisKenneth Y. Yun, David L. Dill. 255-260 [doi]
• Efficient verification of determinate speed-independent circuitsPeter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng. 261-267 [doi]
• Accelerated waveform methods for parallel transient simulation of semiconductor devicesMark W. Reichelt, Andrew Lumsdaine, Jacob K. White. 270-274 [doi]
• An accurate grid local truncation error for device simulationMi-Chang Chang, Jue-Hsien Chern, Ping Yang. 275-282 [doi]
• A relaxation/multipole-accelerated scheme for self-consistent electromechanical analysis of complex 3-D microelectromechanical structuresX. Cai, H. Yie, P. Osterberg, J. Gilbert, Stephen D. Senturia, Jacob K. White. 283-286 [doi]
• The practical application of retiming to the design of high-performance systemsBrian Lockyear, Carl Ebeling. 288-295 [doi]
• Performance-driven partitioning using retiming and replicationLung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku. 296-299 [doi]
• Retiming gated-clocks and precharged circuit structuresAlexander T. Ishii. 300-307 [doi]
• Sequential logic optimization by redundancy addition and removalLuis Entrena, Kwang-Ting Cheng. 310-315 [doi]
• The maximum set of permissible behaviors for FSM networksYosinori Watanabe, Robert K. Brayton. 316-320 [doi]
• Input don t care sequences in FSM networksHuey-Yih Wang, Robert K. Brayton. 321-328 [doi]
• A flexible statistical model for CAD of submicrometer analog CMOS integrated circuitsChristopher Michael, Christopher J. Abel, C. S. Teng. 330-333 [doi]
• Macromodeling of the A.C. characteristics of CMOS Op-ampsPradip Mandal, V. Visvanathan. 334-340 [doi]
• Nyquist data converter testing and yield analysis using behavioral simulationEdward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli. 341-348 [doi]
• Run-time requirement tracingAndrea Casotto. 350-355 [doi]
• A flow-based user interface for efficient execution of the design cycleK. Olav ten Bosch, Pieter van der Wolf, Peter Bingley. 356-363 [doi]
• A visual design environmentEric J. Golin, Annette C. Feng, Linus Huang, Eric Hughes. 364-367 [doi]
• New faster Kernighan-Lin-type graph-partitioning algorithmsShantanu Dutt. 370-377 [doi]
• An algorithm for improving partitions of pin-limited multi-chip systemsMark Beardslee, Alberto L. Sangiovanni-Vincentelli. 378-385 [doi]
• Transforming an arbitrary floorplan into a sliceable oneMajid Sarrafzadeh. 386-389 [doi]
• State look ahead technique for cycle optimization of interacting finite state Moore machinesWolfgang Ecker, M. Hofmeister. 392-397 [doi]
• Retiming sequential circuits for low powerJosé C. Monteiro, Srinivas Devadas, Abhijit Ghosh. 398-402 [doi]
• A symbolic algorithm for maximum flow in 0-1 networksGary D. Hachtel, Fabio Somenzi. 403-406 [doi]
• Generalized constraint generation for analog circuit designEdoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli. 408-414 [doi]
• Latchup-aware placement and parasitic-bounded routing of custom analog cellsBulent Basaran, Rob A. Rutenbar, L. Richard Carley. 415-421 [doi]
• A unified approach to simulating electrical and thermal substrate coupling interactions in ICsNishath K. Verghese, Sang-Soo Lee, David J. Allstot. 422-426 [doi]
• Test generation for path delay faults based on learningIrith Pomeranz, Sudhakar M. Reddy. 428-435 [doi]
• Test generation for multiple faults based on parallel vector pair analysisSeiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita. 436-439 [doi]
• Boolean algebraic test generation using a distributed systemDebashis Bhattacharya, Prathima Agrawal. 440-443 [doi]
• Scheduling a minimum dependence in FSMsSteve C.-Y. Huang, Wayne Wolf. 446-449 [doi]
• High throughput pipelined data path synthesis by conserving the regularity of nested loopsYuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee. 450-453 [doi]
• Execution interval analysis under resource constraintsAdwin H. Timmer, Jochen A. G. Jess. 454-459 [doi]
• Inverter minimization in multi-level logic networksAlok Jain, Randal E. Bryant. 462-465 [doi]
• A simple algorithm for fanout optimization using high-performance buffer librariesK. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati. 466-471 [doi]
• Boolean matching for full-custom ECL gatesRobert N. Mayo, Hervé J. Touati. 472-477 [doi]
• Switch module design with application to two-dimensional segmentation designKai Zhu, D. F. Wong, Yao-Wen Chang. 480-485 [doi]
• Routing for symmetric FPGAs and FPICsYachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu. 486-490 [doi]
• A new generalized row-based global routerWilliam Swartz, Carl Sechen. 491-498 [doi]
• On diagnosis and correction of design errorsIrith Pomeranz, Sudhakar M. Reddy. 500-507 [doi]
• Fault dictionary compression and equivalence class computation for sequential circuitsPaul G. Ryan, W. Kent Fuchs, Irith Pomeranz. 508-511 [doi]
• Tri-state bus conflict checking method for ATPG using BDDYasushi Koseko, Takuji Ogihara, Shinichi Murai. 512-515 [doi]
• Instruction set mapping for performance optimizationMiguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey. 518-521 [doi]
• Quadratic zero-one programming based synthesis of application specific data pathsWerner Geurts, Francky Catthoor, Hugo De Man. 522-525 [doi]
• An ASIP instruction set optimization algorithm with functional module sharing constraintAlauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi. 526-532 [doi]
• Verification of large synthesized designsDaniel Brand. 534-537 [doi]
• HANNIBAL: an efficient tool for logic verification based on recursive learningWolfgang Kunz. 538-543 [doi]
• Probabilistic construction and manipulation of free Boolean diagramsAmelia Shen, Srinivas Devadas, Abhijit Ghosh. 544-583 [doi]
• Tree-based mapping of algorithms to predefined structuresPeter Marwedel. 586-593 [doi]
• Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processorsIng-Jer Huang, Alvin M. Despain. 594-599 [doi]
• Rapid prototyping of microprocessor-based systemsRaj S. Mitra, Biswaroop Guha, Anupam Basu. 600-603 [doi]
• Boolean factorization using multiple-valued minimizationStan Y. Liao, Srinivas Devadas, Abhijit Ghosh. 606-611 [doi]
• Modeling hierarchical combinational circuitsJerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli. 612-617 [doi]
• Analysis of cyclic combinational circuitsSharad Malik. 618-625 [doi]
• Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line modelsQing Zhu, Wayne Wei-Ming Dai, Joe G. Xi. 628-633 [doi]
• Optimal wiresizing under the distributed Elmore delay modelJason Cong, Kwok-Shing Leung. 634-639 [doi]
• An efficient algorithm for the net matching problemRobert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita. 640-644 [doi]
• Logic partitioning to pseudo-exhaustive test for BIST designChien-In Henry Chen, Joel T. Yuen. 646-649 [doi]
• Cellular automata based synthesis of easily and fully testable FSMsDipanwita Roy Chowdhury, Supratik Chakraborty, B. Vamsi, B. Pal Chaudhuri. 650-653 [doi]
• Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boardsMeryem Marzouki, Marcelo Lubaszewski, Mohamed Hedi Touati. 654-657 [doi]
• Sizing and verification of communication buffers for communicating processesTilman Kolks, Bill Lin, Hugo De Man. 660-664 [doi]
• Buffer assignment for data driven architecturesDhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee. 665-668 [doi]
• Exact evaluation of memory size for multi-dimensional signal processing systemsFlorin Balasa, Francky Catthoor, Hugo De Man. 669-672 [doi]
• Maximum projections of don t care conditions in a Boolean networkTed Stanion, Carl Sechen. 674-679 [doi]
• Detection of symmetry of Boolean functions represented by ROBDDsDirk Möller, Janett Mohnke, Michael Weber. 680-684 [doi]
• FGILP: an integer linear program solver based on function graphsYung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula. 685-689 [doi]
• Minimum crosstalk channel routingTong Gao, C. L. Liu. 692-696 [doi]
• A spacing algorithm for performance enhancement and cross-talk reductionKamal Chaudhary, Akira Onozawa, Ernest S. Kuh. 697-702 [doi]
• A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical pathsLih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang. 703-708 [doi]
• Reconfigurable scan chains: a novel approach to reduce test application timeSridhar Narayanan, Melvin A. Breuer. 710-715 [doi]
• Augmented partial resetBen Mathew, Daniel G. Saab. 716-719 [doi]
• Merging multiple FSM controllers for DFT/BIST hardwareDebaditya Mukherjee, Massoud Pedram, Melvin A. Breuer. 720-725 [doi]
• Allocation of multiport memories for hierarchical data streamPaul E. R. Lippens, Jef L. van Meerbergen, Wim F. J. Verhaegh, Albert van der Werf. 728-735 [doi]
• Behavior tables: a basis for system representation and transformational system synthesisKamlesh Rath, M. Esen Tuna, Steven D. Johnson. 736-740 [doi]
• A general consistency technique for increasing the controllability of high level synthesis toolsLawrence F. Arnstein, Donald E. Thomas. 741-744 [doi]
• Efficient modeling of switch-level networks containing undetermined logic node statesPeter Dahlgren, Peter Lidén. 746-752 [doi]
• Piecewise linear models for RsimRussell Kao, Mark Horowitz. 753-758 [doi]
• Parallel multi-delay simulationYun Sik Lee, Peter M. Maurer. 759-762 [doi]
• Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structuresArjan J. van Genderen, N. P. van der Meijs. 764-769 [doi]
• A fast algorithm for VLSI net extractionMario A. Lopez, Ravi Janardan, Sartaj K. Sahni. 770-774 [doi]
• A new feed-through assignment algorithm based on a flow modelTakumi Okamoto, Masaki Ishikawa, Tomoyuki Fujita. 775-778 [doi]