Table of Contents

• Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC DesignDomine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen. [doi]
• Static Scheduling of Multi-Domain Memories For Functional VerificationMurali Kudlugi, Charles Selvidge, Russell Tessier. 2-9 [doi]
• A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor SystemsScott A. Taylor, Carl Ramey, Craig Barner, David Asher. 10-17 [doi]
• Predicting the Performance of Synchronous Discrete Event Simulation SystemsJinsheng Xu, Moon-Jung Chung. 18 [doi]
• System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-ChipTony Givargis, Frank Vahid, Jörg Henkel. 25-30 [doi]
• System Level Design with Spade: an M-JPEG Case StudyPaul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere. 31-38 [doi]
• NetBench: A Benchmarking Suite for Network ProcessorsGokhan Memik, William H. Mangione-Smith, Wendong Hu. 39 [doi]
• A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle ConstraintsXiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong. 49-56 [doi]
• Bus Encoding to Prevent Crosstalk DelayBret M. Victor, Kurt Keutzer. 57 [doi]
• Behavioral Modeling of Analog Circuits by Wavelet Collocation MethodXin Li, Xuan Zeng, Dian Zhou, Xieting Ling. 65-69 [doi]
• Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit SizingWalter Daems, Georges G. E. Gielen, Willy M. C. Sansen. 70-74 [doi]
• Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit MethodYu-Min Lee, Charlie Chung-Ping Chen. 75 [doi]
• Sequential SPFDsSubarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton. 84-90 [doi]
• On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential CircuitsEnrique San Millán, Luis Entrena, José Alberto Espejo. 91-94 [doi]
• Placement Driven Retiming with a Coupled Edge Timing ModelIngmar Neumann, Wolfgang Kunz. 95-102 [doi]
• Solution of Parallel Language Equations for Logic SynthesisNina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli. 103 [doi]
• CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW ProcessorsCagdas Akturan, Margarida F. Jacome. 112-118 [doi]
• Software-Assisted Cache Replacement Mechanisms for Embedded SystemsPrabhat Jain, Srinivas Devadas, Daniel W. Engels, Larry Rudolph. 119-126 [doi]
• Instruction Generation for Hybrid Reconfigurable SystemsRyan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh. 127 [doi]
• Interconnect Resource-Aware Placement for Hierarchical FPGAsAmit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska. 132-136 [doi]
• A Router for Symmetrical FPGAs Based on Exact Routing Density EvaluationNak-Woong Eum, Taewhan Kim, Chong-Min Kyung. 137-143 [doi]
• A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAsVinay Verma, Shantanu Dutt. 144 [doi]
• Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming TechniquesXiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai. 153-157 [doi]
• Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal NetsKaustav Banerjee, Amit Mehrotra. 158-164 [doi]
• Min-Area Retiming on Dynamic Circuit StructuresJason Baumgartner, Andreas Kuehlmann. 176-182 [doi]
• Verification of Integer Multipliers on the Arithmetic Bit LevelDominik Stoffel, Wolfgang Kunz. 183-189 [doi]
• Induction-Based Gate-Level Verification of MultipliersYing-Tsai Chang, Kwang-Ting Cheng. 190 [doi]
• An Assembly-Level Execution-Time Model for Pipelined ArchitecturesGiovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni. 195-200 [doi]
• Improving Memory Energy Using Access Pattern ClassificationMahmut T. Kandemir, Ugur Sezer, Victor Delaluz. 201-206 [doi]
• System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless ChannelsRadu Marculescu, Amit Nandi, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 207 [doi]
• Congestion Aware Layout Driven Logic SynthesisThomas Kutzschebauch, Leon Stok. 216-223 [doi]
• Addressing the Timing Closure Problem by Integrating Logic Optimization and PlacementWilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli. 224-231 [doi]
• Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed InterconnectLuca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob White. 240-244 [doi]
• A Convex Programming Approach to Positive Real Rational ApproximationCarlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira. 245-251 [doi]
• A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined DevicesMichal Rewienski, Jacob White. 252 [doi]
• Low Power System Scheduling and SynthesisNiraj K. Jha. 259-263 [doi]
• Integral Design Representations for Embedded SystemsLothar Thiele. 264 [doi]
• Optimisation Problems for Dynamic Concurrent Task-Based SystemsDiederik Verkest, Peng Yang, Chun Wong, Paul Marchal. 265 [doi]
• Efficient Conflict Driven Learning in Boolean Satisfiability SolverLintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik. 279-285 [doi]
• Partition-Based Decision Heuristics for Image Computation Using SAT and BDDsAarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik. 286-292 [doi]
• Non-linear Quantification Scheduling in Image ComputationPankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang. 293 [doi]
• Symbolic Algebra and Timing Driven Data-flow SynthesisArmita Peymandoust, Giovanni De Micheli. 300-305 [doi]
• Application-Driven Processor Design Exploration for Power-Performance Trade-off AnalysisDiana Marculescu, Anoop Iyer. 306-313 [doi]
• A System for Synthesizing Optimized FPGA Hardware from MATLABMalay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee. 314-319 [doi]
• Behavior-to-Placed RTL Synthesis with Performance-Driven PlacementDaehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi. 320 [doi]
• Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net OrderingJames D. Z. Ma, Lei He. 327-332 [doi]
• Hybrid Structured Clock Network ConstructionHaihua Su, Sachin S. Sapatnekar. 333-336 [doi]
• CASh: A Novel Clock as Shield Design Methodology for Noise Immune Precharge-Evaluate LogicYonghee Im, Kaushik Roy. 337 [doi]
• The Sizing Rules Method for Analog Integrated Circuit DesignHelmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich. 343-349 [doi]
• A Layout-Aware Synthesis Methodology for RF CircuitsPeter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen. 358 [doi]
• On Identifying Don t Care Inputs of Test Patterns for Combinational CircuitsSeiji Kajihara, Kohei Miyase. 364-369 [doi]
• REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic CircuitsChen Wang, Irith Pomeranz, Sudhakar M. Reddy. 370-374 [doi]
• Crosstalk Fault Detection by Dynamic IddXiaoyun Sun, Seonki Kim, Bapiraju Vinnakota. 375 [doi]
• Color Permutation: An Iterative Algorithm for Memory PackingJianwen Zhu, Edward S. Rogers Sr.. 380-383 [doi]
• Constraint Satisfaction for Relative Location Assignment and SchedulingCarlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess. 384-390 [doi]
• A Super-Scheduler for Embedded Reconfigurable SystemsSeda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh. 391 [doi]
• Multilevel Approach to Full-Chip Gridless RoutingJason Cong, Jie Fang, Yan Zhang VI. 396-403 [doi]
• A Force-Directed Maze RouterFan Mo, Abdallah Tabbara, Robert K. Brayton. 404-407 [doi]
• Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability ControlCharles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky. 408 [doi]
• Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank ApproximationJoe Kanapka, Jacob White. 417-423 [doi]
• Fast 3-D Inductance Extraction in Lossy Multi-Layer SubstrateMinqing Liu, Tiejun Yu, Wayne Wei-Ming Dai. 424-429 [doi]
• Simulation Approaches for Strongly Coupled Interconnect SystemsJoel R. Phillips, Luis Miguel Silveira. 430 [doi]
• BOOM - A Heuristic Boolean MinimizerJan Hlavicka, Petr Fiser. 439-442 [doi]
• Faster SAT and Smaller BDDs via Common Function StructureFadi A. Aloul, Igor L. Markov, Karem A. Sakallah. 443-448 [doi]
• Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic CircuitsRupesh S. Shelar, Sachin S. Sapatnekar. 449-452 [doi]
• A Probabilistic Constructive Approach to Optimization ProblemsJennifer L. Wong, Farinaz Koushanfar, Seapahn Meguerdichian, Miodrag Potkonjak. 453 [doi]
• Energy Efficient Real-Time SchedulingAmit Sinha, Anantha Chandrakasan. 458-470 [doi]
• Efficient Performance Estimation for General Real-Time Task SystemsHongchao (Stephanie) Liu, Xiaobo Hu. 464-470 [doi]
• Multigrid-Like Technique for Power Grid AnalysisJoseph N. Kozhaya, Sani R. Nassif, Farid N. Najm. 480-487 [doi]
• An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic SystemsDaler N. Rakhmatov, Sarma B. K. Vrudhula. 488-493 [doi]
• Power-Delay Modeling of Dynamic CMOS Gates for Circuit OptimizationJosé Luis Rosselló, Jaume Segura. 494 [doi]
• A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom MacrocellsClayton B. McDonald, Randal E. Bryant. 501-506 [doi]
• On the Signal Bounding Problem in Timing AnalysisJin-fuw Lee, Daniel L. Ostapko, Jeffery Soreff, C. K. Wong. 507-514 [doi]
• False-Noise Analysis using Logic ImplicationsAlexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov. 515 [doi]
• The Design and Optimization of SOC Test SolutionsErik Larsson, Zebo Peng, Gunnar Carlsson. 523-530 [doi]
• Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL SaboteursDonald B. Shaw, Dhamin Al-Khalili, Come Rozon. 531-536 [doi]
• Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection TechniqueKaijie Wu, Ramesh Karri. 537 [doi]
• An Integrated Data Path Optimization for Low Power Based on Network Flow MethodChun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu. 553-559 [doi]
• What is the Limit of Energy Saving by Dynamic Voltage Scaling?Gang Qu. 560 [doi]
• Congestion Reduction During Placement Based on Integer ProgrammingXiaojian Yang, Ryan Kastner, Majid Sarrafzadeh. 573-576 [doi]
• Direct Transistor-Level Layout for Digital BlocksPrakash Gopalakrishnan, Rob A. Rutenbar. 577 [doi]
• Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced TruncationPayam Heydari, Massoud Pedram. 586-591 [doi]
• Improving the Robustness of a Surface Integral Formulation for Wideband Impendance Extraction of 3D StructuresZhenhai Zhu, Jingfang Huang, Ben Song, Jacob White. 592-597 [doi]
• Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated CircuitsSteven C. Chan, Kenneth L. Shepard. 598 [doi]
• Single-Pass Redundancy Addition and RemovalChih-Wei Jim Chang, Malgorzata Marek-Sadowska. 606-609 [doi]
• Efficient Canonical Form for Boolean Matching of Complex Functions in Large LibrariesJovanka Ciric, Carl Sechen. 610-617 [doi]
• Compatible Observability Don t Cares RevisitedRobert K. Brayton. 618 [doi]
• A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISAAndreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr. 625-630 [doi]
• Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable EncodingSubash G. Chandar, Mahesh Mehendale, R. Govindarajan. 631-634 [doi]
• I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy EfficiencySri Parameswaran, Jörg Henkel. 635 [doi]
• IC Power Distribution ChallengesSudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu. 643-650 [doi]
• Challenges in Power-Ground IntegrityShen Lin, Norman Chang. 651 [doi]
• Automatic Hierarchical Design: Fantasy or Reality? (Panel)Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni. 656 [doi]