Table of Contents

• A Cell-Replicating Approach to Minicut-Based Circuit PartitioningChuck Kring, A. Richard Newton. 2-5
• On Clustering for Minimum Delay/AreaRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 6-9
• Fast Spectral Methods for Ratio Cut Partitioning and ClusteringLars W. Hagen, Andrew B. Kahng. 10-13
• iMACSIM: A Program for Multi-Level Analog Circuit SimulationJaidip Singh, Resve A. Saleh. 16-19
• A Modified Envelope-Following Approach to Clocked Analog Circuit SimulationLuis Miguel Silveira, Jacob White, Steven Leeb. 20-23
• An Accelerated Steady-State Method for Networks with Internally Controlled SwitchesDavid Bedrosian, Jiri Vlach. 24-27
• Automatic Synthesis of Time-Stationary Controllers for Pipelined Data PathsJames J. Kim, Fadi J. Kurdahi, Nohbyung Park. 30-33
• Layout-Area Models for High-Level SynthesisAllen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski. 34-37
• Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated CircuitsShi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu. 38-41
• A New Performance Driven Placement AlgorithmTong Gao, Pravo M. Vaidya, C. L. Liu. 44-47
• Wafer Packing for Full Mask Exposure FabricationChing-Ting Wu, Andrew Lim, David Hung-Chang Du. 52-55
• A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block ShapingSang-Gil Choi, Chong-Min Kyung. 56-59
• An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect SimulationJaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson. 62-65
• Delay and Crosstalk Simulation of High-Speed VLSI Interconnects with Nonlinear TerminationsDong H. Xie, Michel S. Nakhla. 66-69
• Evaluating RC-Interconnect Using Moment-Matching ApproximationsNanda Gopal, Dean P. Neikirk, Lawrence T. Pillage. 74-77
• The Effects of False Paths in High-Level SynthesisReinaldo A. Bergamaschi. 80-83
• A Scheduling Algorithm for Conditional Resource SharingTaewhan Kim, Jane W.-S. Liu, C. L. Liu. 84-87
• Optimizing Resource Utilization Using TransformationsMiodrag Potkonjak, Jan M. Rabaey. 88-91
• An Algorithm for Component Selection in Performance Optimized SchedulingLoganath Ramachandran, Daniel Gajski. 92-95
• Flexible Block-Multiplier GenerationH. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok. 106-109
• Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and ApplicationsKartikeya Mayaram, Ping Yang, Jue-Hsien Chern. 112-115
• Conjugate Direction Waveform Methods for Transient Two-Dimensional Simulation for MOS DevicesAndrew Lumsdaine, Mark W. Reichelt, Jacob White. 116-119
• Transient Sensitivity Computation for Waveform Relaxation Based Timing SimulationChun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng. 120-123
• Heuristic Minimazation of Multiple-Valued RelationsYosinori Watanabe, Robert K. Brayton. 126-129
• LSAT-An Algorithm for the Synthesis of Two Level Threshold Gate NetworksArlindo L. Oliveira, Alberto L. Sangiovanni-Vincentelli. 130-133
• Layout Driven Logic Restructuring/DecompositionMassoud Pedram, Narasimha B. Bhat. 134-137
• Data Framework for VLSI DesignAmir Milo, Smadar Nehab. 140-143
• SLIM: A System for ASIC Library ManagementMahesh Mehendale, P. Murugavel, M. Poornima. 144-147
• Estimating Essential Design Characteristics to Support Project Planning for ASIC Design ManagementKlaus D. Müller-Glaser, K. Kirsch, K. Neusinger. 148-151
• Rapid-Prototyping of Hardware and Software in a Unified FrameworkMani B. Srivastava, Robert W. Brodersen. 152-155
• Improved Methods for IC Yield and Quality Optimization Using Surface IntegralsPeter Feldmann, Stephen W. Director. 158-161
• New Simulation Methods for MOS VLSI Timing and ReliabilityYung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang. 162-165
• Circuit Optimization Driven by Worst-Case DistancesKurt Antreich, Helmut E. Graeb. 166-169
• Circuit Performance Variability Reduction: Principles, Problems, and Practical SolutionsM. A. Styblinski, J. C. Zhang. 170-173
• Delay Computation in Combinational Logic Circuits: Theory and AlgorithmsSrinivas Devadas, Kurt Keutzer, Sharad Malik. 176-179
• Timing Analysis and Delay-Fault Test Generation using Path-Recursive FunctionsPatrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 180-183
• Performance Enhancement through the Generalized Bypass TransformPatrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni. 184-187
• Delay Optimization of Combinational Logic Circuits By Clustering and Partial CollapsingHervé J. Touati, Hamid Savoj, Robert K. Brayton. 188-191
• DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational CircuitsTorsten Grüning, Udo Mahlstedt, Hartmut Koopmeiners. 194-197
• Knowledge-Based Debugging of ASICs: Real Case Study and Performance AnalysisM. Marzouki, F. L. Vargas. 198-201
• BETA: Behavioral Testability AnalysisChung-Hsing Chen, Chienwen Wu, Daniel G. Saab. 202-205
• Path Sensitization in Critical Path ProblemHsi-Chuan Chen, David Hung-Chang Du. 208-211
• FPD - An Environment for Exact Timing AnalysisJoão P. Marques Silva, Karem A. Sakallah, Luís M. Vidigal. 212-215
• A New Approach to Solving False Path Problem in Timing AnalysisShiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu. 216-219
• State Assignment Based on the Reduced Dependency Theory and Recent Experimental ResultsChristopher Duff, Gabriele Saucier. 222-225
• A Flexible Scheme for State Assignment Based on Characteristics of the FSMBiswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri. 226-229
• Encoding Multiple Outputs for Improved Column CompactionDavid Binger, David Knapp. 230-233
• Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST HardwareDebaditya Mukherjee, Charles Njinda, Melvin A. Breuer. 236-239
• BISTSYN - A Built-In Self-Test SynthesizerChien-In Henry Chen. 240-243
• Comparison of Random Test Vector Generation StrategiesWarren H. Debany Jr., Carlos R. P. Hartmann, Pramod K. Varshney, Kishan G. Mehrotra. 244-247
• Built-In Self-Test for Multi-Port RAMsVladimir Castro Alves, Michael Nicolaidis, P. Lestrat, Bernard Courtois. 248-251
• The Hercules CAD Task Management SystemJay B. Brockman, Stephen W. Director. 254-257
• The Configuration Management for Version Control in an Object-Oriented VHDL Design EnvironmentMoon-Jung Chung, Sangchul Kim. 258-261
• SADE: A Graphical Tool for VHDL-Based System AnalysisJukka Lahti, Matti Sipola, Jorma Kivelä. 262-265
• System Specification and Synthesis with the SpecCharts LanguageSanjiv Narayan, Frank Vahid, Daniel Gajski. 266-269
• Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC MemoryJ. Vanhoof, Ivo Bolsens, Hugo De Man. 272-275
• Post-Processor for Data Path Synthesis Using Multiport MemoriesImtiaz Ahmad, C. Y. Roger Chen. 276-279
• Clustering Techniques for Register Optimization During Scheduling PreprocessingFrancis Depuydt, Gert Goossens, Hugo De Man. 280-283
• Scheduling in Programmable Video Signal ProcessorsGerben Essink, Emile H. L. Aarts, R. van Dongen, P. van Gerwen, Jan H. M. Korst, Kees A. Vissers. 284-287
• Circuit Comparison by Hierarchical Pattern MatchingGeorg Pelz, Uli Roettcher. 290-293
• HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect DesignsKeh-Jeng Chang, Soo-Young Oh, Ken Lee. 294-297
• Hierarchical Analyzer for VLSI Power Supply Networks Based on a New Reduction MethodTakeshi Yoshitome. 298-301
• Automatic Detection of MOS Synchronizers for Timing VerificationJoel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff. 304-307
• Static Timing Analysis Using Interval ConstraintsRonald Stewart, Jacques Benkoski. 308-311
• The Calculation of Signal Stable Ranges in Combinational CircuitsLi-Ren Liu, Hsi-Chuan Chen, David Hung-Chang Du. 312-315
• Automatic Synthesis of Locally-Clocked Asynchronous State MachinesSteven M. Nowick, David L. Dill. 318-321
• Synthesis of Hazard-Free Asynchronous Circuits from Graphical SpecificationsCho W. Moon, Paul R. Stephan, Robert K. Brayton. 322-325
• Synthesis for Testability Techniques for Asynchronous CircuitsKurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 326-329
• Timing-Oriented Routers for PCB Layout Design of High-Performance ComputersYutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani. 332-335
• Exact Zero SkewRen-Song Tsay. 336-339
• PROTON: A Parallel Detailed Router on an MIMD Parallel MachineTsukasa Yamauchi, Akio Ishizuka, Toshiyuki Nakata, Nobuyuki Nishiguchi, Nobuhiko Koike. 340-343
• Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic AnalysisRandal E. Bryant. 350-353
• Bipolar Timing Modeling Including Interconnects Based on Parametric CorrectionAndrew T. Yang, Yu-Hsu Chang. 354-357
• A Stimulus/Response System Based on Hierarchical Timing DiagramsKarim Khordoc, Mario Dufresne, Eduard Cerny. 358-361
• Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift TransformationFrank Vahid, Daniel Gajski. 362-365
• Converting Combinational Circuits into Pipelined Data PathsAndreas Münzner, Günter Hemme. 368-371
• An ATPG-Based Approach to Sequential Logic OptimizationKwang-Ting Cheng. 372-375
• Calculating Resetability and Reset SequencesCarl Pixley, Gary Beihl. 376-379
• Verification of Relations Between Synchronous MachinesFilip Van Aelten, Jonathan Allen, Srinivas Devadas. 380-383
• A Behavioral Representation for Nyquist Rate A/D ConvertersEdward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli, Georges G. E. Gielen, Paul R. Gray. 386-389
• Automating Analog Circuit Design using Constrained Optimization TechniquesPrabir C. Maulik, L. Richard Carley. 390-393
• Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM IIJohn M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley. 394-397
• A Fault Oriented Partial Scan Design ApproachVivek Chickermane, Janak H. Patel. 400-403
• Timing-Driven Partial ScanJing-Yang Jou, Kwang-Ting Cheng. 404-407
• Ordering Storage Elements in a Single Scan ChainRajesh Gupta, Melvin A. Breuer. 408-411
• Finite State Machine Decomposition by Transition PairingJames H. Kukula, Srinivas Devadas. 414-417
• Don t Care Sequences and the Optimization of Interacting Finite State MachinesJune-Kyung Rho, Gary D. Hachtel, Fabio Somenzi. 418-421
• An Automatic Finite State Machine Synthesis Using Temporal Logic DecompositionKeisuke Bekki, Tohru Nagai, Nobuhiro Hamada, Tsuguo Shimizu, Noriharu Hiratsuka, Kazumasa Shima. 422-425
• Algorithms for Three-Layer Over-The-Cell Channel RoutingNancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh. 428-431
• A New Model for Over-The-Cell Channel Routing with Three LayersMasayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato. 432-435
• A Channel Router for Single Layer Customization TechnologyYachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu. 436-439
• A Hierarchical Methodology to Improve Channel Routing by Pin PermutationCliff Yungchin Hou, C. Y. Roger Chen. 440-443
• A New Test Generation Method for Sequential CircuitsDong-Ho Lee, Sudhakar M. Reddy. 446-449
• Test Generation for Synchronous Sequential Circuits Based on Fault ExtractionIrith Pomeranz, Sudhakar M. Reddy. 450-453
• Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test StrategyIrith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy. 454-457
• A Signal-Driven Discrete Relaxation Technique for Architectural Level Test GenerationJaushin Lee, Janak H. Patel. 458-461
• Extended BDD s: Trading off Canonicity for Structure in Verification AlgorithmsSeh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi. 464-467
• Probabilistic Design VerificationJawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham. 468-471
• Minimazation of Binary Decision Diagrams Based on Exchanges of VariablesNagisa Ishiura, Hiroshi Sawada, Shuzo Yajima. 472-475
• Variable Ordering and Selection for FSM TraversalSeon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi. 476-479
• A Convex Optimization Approach to Transistor Sizing for CMOS CircuitsSachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya. 482-485
• A New Linear Placement Algorithm for Cell GenerationEdgar Auer, Werner L. Schiele, Georg Sigl. 486-489
• Two-Dimensional Layout Synthesis for Large-Scale CMOS CircuitsKatsunori Tani, Kyoichi Izumi, Masahiko Kashimura, Tsuneo Matsuda, Takashi Fujii. 490-493
• A Systematic Approach for Designing Testable VLSI CircuitsSen-Pin Lin, Charles Njinda, Melvin A. Breuer. 496-499
• Design for Easily Applying Test Vectors to Improve Delay Fault CoverageEdwin Hsing-Mean Sha, Liang-Fang Chao. 500-503
• Application of Boolean Unification to Combinational Logic SynthesisMasahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen. 510-513
• Extracting Local Don t Cares for Network OptimizationHamid Savoj, Robert K. Brayton, Hervé J. Touati. 514-517
• Observability Relations and Observability Don t CaresHamid Savoj, Robert K. Brayton. 518-521
• Minimizing Channel Density by Shifting Blocks and TerminalsYang Cai, D. F. Wong. 524-527
• The Crossing Distribution ProblemMalgorzata Marek-Sadowska, Majid Sarrafzadeh. 528-531
• On Topological Via Minimization and RoutingMoazzem Hossain, Naveed A. Sherwani. 532-535
• Switchbox Steiner Tree Problem in Presence of ObstaclesS. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani. 536-539
• Methods for Reducing Events in Sequential Circuit Fault SimulationElizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel. 546-549
• Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault SetsNoriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima. 550-553
• A Switch-Level Matrix Approach to Transistor-Level Fault SimulationTerry Lee, Ibrahim N. Hajj. 554-557
• Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAsMasahiro Fujita, Yusuke Matsunaga. 560-563
• Improved Logic Synthesis Algorithms for Table Look Up ArchitecturesRajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 564-567
• Technology Mapping on Lookup Table-Based FPGAs for PerformanceRobert J. Francis, Jonathan Rose, Zvonko G. Vranesic. 568-571
• Performance Directed Synthesis for Table Look Up Programmable Gate ArraysRajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 572-575