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ICCAD

ICCAD. 1991.

Conference: iccad 1991

Abstract

Abstract is missing.

Table of Contents

2-5A Cell-Replicating Approach to Minicut-Based Circuit Partitioning
Chuck Kring, A. Richard Newton
6-9On Clustering for Minimum Delay/Area
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
10-13Fast Spectral Methods for Ratio Cut Partitioning and Clustering
Lars W. Hagen, Andrew B. Kahng
16-19iMACSIM: A Program for Multi-Level Analog Circuit Simulation
Jaidip Singh, Resve A. Saleh
20-23A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation
Luis Miguel Silveira, Jacob White, Steven Leeb
24-27An Accelerated Steady-State Method for Networks with Internally Controlled Switches
David Bedrosian, Jiri Vlach
30-33Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths
James J. Kim, Fadi J. Kurdahi, Nohbyung Park
34-37Layout-Area Models for High-Level Synthesis
Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski
38-41Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits
Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu
44-47A New Performance Driven Placement Algorithm
Tong Gao, Pravo M. Vaidya, C. L. Liu
52-55Wafer Packing for Full Mask Exposure Fabrication
Ching-Ting Wu, Andrew Lim, David Hung-Chang Du
56-59A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping
Sang-Gil Choi, Chong-Min Kyung
62-65An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation
Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson
66-69Delay and Crosstalk Simulation of High-Speed VLSI Interconnects with Nonlinear Terminations
Dong H. Xie, Michel S. Nakhla
74-77Evaluating RC-Interconnect Using Moment-Matching Approximations
Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage
80-83The Effects of False Paths in High-Level Synthesis
Reinaldo A. Bergamaschi
84-87A Scheduling Algorithm for Conditional Resource Sharing
Taewhan Kim, Jane W.-S. Liu, C. L. Liu
88-91Optimizing Resource Utilization Using Transformations
Miodrag Potkonjak, Jan M. Rabaey
92-95An Algorithm for Component Selection in Performance Optimized Scheduling
Loganath Ramachandran, Daniel Gajski
106-109Flexible Block-Multiplier Generation
H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok
112-115Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern
116-119Conjugate Direction Waveform Methods for Transient Two-Dimensional Simulation for MOS Devices
Andrew Lumsdaine, Mark W. Reichelt, Jacob White
120-123Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation
Chun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng
126-129Heuristic Minimazation of Multiple-Valued Relations
Yosinori Watanabe, Robert K. Brayton
130-133LSAT-An Algorithm for the Synthesis of Two Level Threshold Gate Networks
Arlindo L. Oliveira, Alberto L. Sangiovanni-Vincentelli
134-137Layout Driven Logic Restructuring/Decomposition
Massoud Pedram, Narasimha B. Bhat
140-143Data Framework for VLSI Design
Amir Milo, Smadar Nehab
144-147SLIM: A System for ASIC Library Management
Mahesh Mehendale, P. Murugavel, M. Poornima
148-151Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management
Klaus D. Müller-Glaser, K. Kirsch, K. Neusinger
152-155Rapid-Prototyping of Hardware and Software in a Unified Framework
Mani B. Srivastava, Robert W. Brodersen
158-161Improved Methods for IC Yield and Quality Optimization Using Surface Integrals
Peter Feldmann, Stephen W. Director
162-165New Simulation Methods for MOS VLSI Timing and Reliability
Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang
166-169Circuit Optimization Driven by Worst-Case Distances
Kurt Antreich, Helmut E. Graeb
170-173Circuit Performance Variability Reduction: Principles, Problems, and Practical Solutions
M. A. Styblinski, J. C. Zhang
176-179Delay Computation in Combinational Logic Circuits: Theory and Algorithms
Srinivas Devadas, Kurt Keutzer, Sharad Malik
180-183Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions
Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
184-187Performance Enhancement through the Generalized Bypass Transform
Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni
188-191Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing
Hervé J. Touati, Hamid Savoj, Robert K. Brayton
194-197DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
Torsten Grüning, Udo Mahlstedt, Hartmut Koopmeiners
198-201Knowledge-Based Debugging of ASICs: Real Case Study and Performance Analysis
M. Marzouki, F. L. Vargas
202-205BETA: Behavioral Testability Analysis
Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab
208-211Path Sensitization in Critical Path Problem
Hsi-Chuan Chen, David Hung-Chang Du
212-215FPD - An Environment for Exact Timing Analysis
João P. Marques Silva, Karem A. Sakallah, Luís M. Vidigal
216-219A New Approach to Solving False Path Problem in Timing Analysis
Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu
222-225State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results
Christopher Duff, Gabriele Saucier
226-229A Flexible Scheme for State Assignment Based on Characteristics of the FSM
Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
230-233Encoding Multiple Outputs for Improved Column Compaction
David Binger, David Knapp
236-239Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware
Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer
240-243BISTSYN - A Built-In Self-Test Synthesizer
Chien-In Henry Chen
244-247Comparison of Random Test Vector Generation Strategies
Warren H. Debany Jr., Carlos R. P. Hartmann, Pramod K. Varshney, Kishan G. Mehrotra
248-251Built-In Self-Test for Multi-Port RAMs
Vladimir Castro Alves, Michael Nicolaidis, P. Lestrat, Bernard Courtois
254-257The Hercules CAD Task Management System
Jay B. Brockman, Stephen W. Director
258-261The Configuration Management for Version Control in an Object-Oriented VHDL Design Environment
Moon-Jung Chung, Sangchul Kim
262-265SADE: A Graphical Tool for VHDL-Based System Analysis
Jukka Lahti, Matti Sipola, Jorma Kivelä
266-269System Specification and Synthesis with the SpecCharts Language
Sanjiv Narayan, Frank Vahid, Daniel Gajski
272-275Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory
J. Vanhoof, Ivo Bolsens, Hugo De Man
276-279Post-Processor for Data Path Synthesis Using Multiport Memories
Imtiaz Ahmad, C. Y. Roger Chen
280-283Clustering Techniques for Register Optimization During Scheduling Preprocessing
Francis Depuydt, Gert Goossens, Hugo De Man
284-287Scheduling in Programmable Video Signal Processors
Gerben Essink, Emile H. L. Aarts, R. van Dongen, P. van Gerwen, Jan H. M. Korst, Kees A. Vissers
290-293Circuit Comparison by Hierarchical Pattern Matching
Georg Pelz, Uli Roettcher
294-297HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs
Keh-Jeng Chang, Soo-Young Oh, Ken Lee
298-301Hierarchical Analyzer for VLSI Power Supply Networks Based on a New Reduction Method
Takeshi Yoshitome
304-307Automatic Detection of MOS Synchronizers for Timing Verification
Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff
308-311Static Timing Analysis Using Interval Constraints
Ronald Stewart, Jacques Benkoski
312-315The Calculation of Signal Stable Ranges in Combinational Circuits
Li-Ren Liu, Hsi-Chuan Chen, David Hung-Chang Du
318-321Automatic Synthesis of Locally-Clocked Asynchronous State Machines
Steven M. Nowick, David L. Dill
322-325Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications
Cho W. Moon, Paul R. Stephan, Robert K. Brayton
326-329Synthesis for Testability Techniques for Asynchronous Circuits
Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
332-335Timing-Oriented Routers for PCB Layout Design of High-Performance Computers
Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani
336-339Exact Zero Skew
Ren-Song Tsay
340-343PROTON: A Parallel Detailed Router on an MIMD Parallel Machine
Tsukasa Yamauchi, Akio Ishizuka, Toshiyuki Nakata, Nobuyuki Nishiguchi, Nobuhiko Koike
350-353Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
Randal E. Bryant
354-357Bipolar Timing Modeling Including Interconnects Based on Parametric Correction
Andrew T. Yang, Yu-Hsu Chang
358-361A Stimulus/Response System Based on Hierarchical Timing Diagrams
Karim Khordoc, Mario Dufresne, Eduard Cerny
362-365Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation
Frank Vahid, Daniel Gajski
368-371Converting Combinational Circuits into Pipelined Data Paths
Andreas Münzner, Günter Hemme
372-375An ATPG-Based Approach to Sequential Logic Optimization
Kwang-Ting Cheng
376-379Calculating Resetability and Reset Sequences
Carl Pixley, Gary Beihl
380-383Verification of Relations Between Synchronous Machines
Filip Van Aelten, Jonathan Allen, Srinivas Devadas
386-389A Behavioral Representation for Nyquist Rate A/D Converters
Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli, Georges G. E. Gielen, Paul R. Gray
390-393Automating Analog Circuit Design using Constrained Optimization Techniques
Prabir C. Maulik, L. Richard Carley
394-397Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II
John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley
400-403A Fault Oriented Partial Scan Design Approach
Vivek Chickermane, Janak H. Patel
404-407Timing-Driven Partial Scan
Jing-Yang Jou, Kwang-Ting Cheng
408-411Ordering Storage Elements in a Single Scan Chain
Rajesh Gupta, Melvin A. Breuer
414-417Finite State Machine Decomposition by Transition Pairing
James H. Kukula, Srinivas Devadas
418-421Don t Care Sequences and the Optimization of Interacting Finite State Machines
June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi
422-425An Automatic Finite State Machine Synthesis Using Temporal Logic Decomposition
Keisuke Bekki, Tohru Nagai, Nobuhiro Hamada, Tsuguo Shimizu, Noriharu Hiratsuka, Kazumasa Shima
428-431Algorithms for Three-Layer Over-The-Cell Channel Routing
Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
432-435A New Model for Over-The-Cell Channel Routing with Three Layers
Masayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato
436-439A Channel Router for Single Layer Customization Technology
Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu
440-443A Hierarchical Methodology to Improve Channel Routing by Pin Permutation
Cliff Yungchin Hou, C. Y. Roger Chen
446-449A New Test Generation Method for Sequential Circuits
Dong-Ho Lee, Sudhakar M. Reddy
450-453Test Generation for Synchronous Sequential Circuits Based on Fault Extraction
Irith Pomeranz, Sudhakar M. Reddy
454-457Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy
Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy
458-461A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation
Jaushin Lee, Janak H. Patel
464-467Extended BDD s: Trading off Canonicity for Structure in Verification Algorithms
Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
468-471Probabilistic Design Verification
Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham
472-475Minimazation of Binary Decision Diagrams Based on Exchanges of Variables
Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima
476-479Variable Ordering and Selection for FSM Traversal
Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
482-485A Convex Optimization Approach to Transistor Sizing for CMOS Circuits
Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya
486-489A New Linear Placement Algorithm for Cell Generation
Edgar Auer, Werner L. Schiele, Georg Sigl
490-493Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits
Katsunori Tani, Kyoichi Izumi, Masahiko Kashimura, Tsuneo Matsuda, Takashi Fujii
496-499A Systematic Approach for Designing Testable VLSI Circuits
Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
500-503Design for Easily Applying Test Vectors to Improve Delay Fault Coverage
Edwin Hsing-Mean Sha, Liang-Fang Chao
510-513Application of Boolean Unification to Combinational Logic Synthesis
Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
514-517Extracting Local Don t Cares for Network Optimization
Hamid Savoj, Robert K. Brayton, Hervé J. Touati
518-521Observability Relations and Observability Don t Cares
Hamid Savoj, Robert K. Brayton
524-527Minimizing Channel Density by Shifting Blocks and Terminals
Yang Cai, D. F. Wong
528-531The Crossing Distribution Problem
Malgorzata Marek-Sadowska, Majid Sarrafzadeh
532-535On Topological Via Minimization and Routing
Moazzem Hossain, Naveed A. Sherwani
536-539Switchbox Steiner Tree Problem in Presence of Obstacles
S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani
546-549Methods for Reducing Events in Sequential Circuit Fault Simulation
Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel
550-553Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets
Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima
554-557A Switch-Level Matrix Approach to Transistor-Level Fault Simulation
Terry Lee, Ibrahim N. Hajj
560-563Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs
Masahiro Fujita, Yusuke Matsunaga
564-567Improved Logic Synthesis Algorithms for Table Look Up Architectures
Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
568-571Technology Mapping on Lookup Table-Based FPGAs for Performance
Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
572-575Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
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