Abstract is missing.
- Organizing Committee [doi]
- Program Committee [doi]
- Welcome Message [doi]
- Additional Reviewers [doi]
- Computer Architecture in the Many-Core EraWilliam J. Dally. 1 [doi]
- Scaling Manufacturability Software to Thousands of ProcessorsFabio Angelillis. 2 [doi]
- Long-term Performance Bottleneck Analysis and PredictionFei Gao, Suleyman Sair. 3-9 [doi]
- Speculative Code Value Specialization Using the Trace Cache Fill UnitWeifeng Zhang, Brad Calder, Dean M. Tullsen, Steve Checkoway. 10-16 [doi]
- Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address BusesJiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra. 17-24 [doi]
- Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft IndexingShuo Wang, Lei Wang. 25-30 [doi]
- A Low Power Highly Associative Cache for Embedded SystemsChuanjun Zhang. 31-36 [doi]
- On the Improvement of Statistical Static Timing AnalysisRajesh Garg, Nikhil Jayakumar, Sunil P. Khatri. 37-42 [doi]
- FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with CouplingDebasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack. 43-49 [doi]
- Reduction of Crosstalk Pessimism using Tendency Graph ApproachMurthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier. 50-55 [doi]
- Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial CorrelationNing Mi, Jeffrey Fan, Sheldon X.-D. Tan. 56-62 [doi]
- RasP: An Area-efficient, On-chip NetworkSimon Hollis, Simon W. Moore. 63-69 [doi]
- Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free InterconnectsYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye. 70-75 [doi]
- CMOS Comparators for High-Speed and Low-Power ApplicationsEric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri. 76-81 [doi]
- Reconfigurable CAM Architecture for Network Search EnginesMehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara. 82-87 [doi]
- Delay and Area Efficient First-level Cache Soft Error Detection and CorrectionKarl Mohr, Lawrence Clark. 88-92 [doi]
- Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CADKrishnendu Chakrabarty. 93-100 [doi]
- Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache EnergyDan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum. 101-107 [doi]
- Customizable Fault Tolerant Caches for Embedded ProcessorsSubramanian Ramaswamy, Sudhakar Yalamanchili. 108-113 [doi]
- Reduce Register Files Leakage Through Discharging CellsLingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang. 114-119 [doi]
- Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread ExecutionYi Ma, Huiyang Zhou. 120-126 [doi]
- Dynamic Co-Processor Architecture for Software Acceleration on CSoCsAbhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar. 127-133 [doi]
- Polaris: A System-Level Roadmap for On-Chip Interconnection NetworksVassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh. 134-141 [doi]
- A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-ChipsDara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad. 142-147 [doi]
- Perceptron Based Consumer Prediction in Shared-Memory MultiprocessorsSean Leventhal, Manoj Franklin. 148-154 [doi]
- A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep SignalsKimiyoshi Usami, Naoaki Ohkubo. 155-161 [doi]
- Synthesis of Regular Logic Bricks for Robust IC DesignKim Yaw Tong, Lawrence T. Pileggi. 162-167 [doi]
- An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply NetworksSanjay Pant, David Blaauw. 168-173 [doi]
- Implementing Tile-based Chip Multiprocessors with GALS Clocking StylesZhiyi Yu, Bevan M. Baas. 174-179 [doi]
- Scale in Chip Interconnect requires Network Technology Enno Wein. 180-186 [doi]
- Interconnect Considerations For High Performance Network on Chip DesignsUri Cummings. 187 [doi]
- Addressing Multicore Communication Challenges Using NoC TechnologyDrew Wingard. 188 [doi]
- Clustering-Based Microcode CompressionEdson Borin, Mauricio Breternitz Jr., Youfeng Wu, Guido Araujo. 189-196 [doi]
- Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based SchedulingKuo-Su Hsiao, Chung-Ho Chen. 197-202 [doi]
- An Enhancement for a Scheduling Logic Pipelined over two Cycles Ruben Gran, Enric Morancho, Àngel Olivé, José MarÃa LlaberÃa. 203-209 [doi]
- Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic GatesSaraju P. Mohanty, Elias Kougianos. 210-215 [doi]
- Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTIKunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy. 216-221 [doi]
- Interconnect Matching Design Rule Inferring and Optimization through Correlation ExtractionRasit Onur Topaloglu, Andrew B. Kahng. 222-229 [doi]
- Power-Constrained SOC Test Schedules through Utilization of Functional BusesFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara. 230-236 [doi]
- RTL Scan Design for Skewed-Load At-speed Test under Power ConstraintsHo Fai Ko, Nicola Nicolici. 237-242 [doi]
- Power Droop TestingIlia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker. 243-250 [doi]
- Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test GenerationXiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja. 251-258 [doi]
- Scalable Sequential Equivalence Checking across Arbitrary Design Transformations Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen. 259-266 [doi]
- Seqver : A Sequential Equivalence Verifier for Hardware Designs Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili. 267-273 [doi]
- High-Level vs. RTL Combinational Equivalence: An IntroductionAlan Hu. 274-279 [doi]
- Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation TechniqueKameshwar Chandrasekar, Michael S. Hsiao. 280-285 [doi]
- Requirements and Concepts for Transaction Level AssertionsWolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten. 286-293 [doi]
- Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon DebugMarc Boule, Jean-Samuel Chenard, Zeljko Zilic. 294-299 [doi]
- Simulation-based functional test justification using a decision-digram-based Boolean data minerCharles H.-P. Wen, Onur Guzey, Li-C. Wang. 300-307 [doi]
- FPGA Implementation of High Speed FIR Filters Using Add and Shift MethodShahnam Mirzaei, Anup Hosangadi, Ryan Kastner. 308-313 [doi]
- FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic SystemsOsama Al-Khaleel, Christos A. Papachristou, Frank Wolff, Kiamal Z. Pekmestzi. 314-319 [doi]
- Split-Row: A Reduced Complexity, High Throughput LDPC Decoder ArchitectureTinoosh Mohsenin, Bevan M. Baas. 320-325 [doi]
- An Efficient, Scalable Hardware Engine for Boolean SATisfiabilityMandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi. 326-331 [doi]
- Power/ground supply network optimization for power-gatingHailin Jiang, Malgorzata Marek-Sadowska. 332-337 [doi]
- A Pattern Generation Technique for Maximizing Power Supply CurrentsKunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu. 338-343 [doi]
- Partial Functional Manipulation Based Wirelength MinimizationAvijit Dutta, David Z. Pan. 344-349 [doi]
- Iterative-Constructive Standard Cell Placer for High Speed and Low PowerSungjae Kim, Eugene Shragowitz. 350-355 [doi]
- Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski. 356-361 [doi]
- Assertion-Based Microarchitecture Design for Improved ReliabilityVimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi. 362-369 [doi]
- High-speed Factorization Architecture for Soft-decision Reed-Solomon DecodingXinmiao Zhang. 370-375 [doi]
- Guiding Architectural SRAM ModelsBanit Agrawal, Timothy Sherwood. 376-382 [doi]
- A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical ModelsJinwen Xi, Peixin Zhong. 383-388 [doi]
- Reliability Support for On-Chip Memories Using Networks-on-ChipFederico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 389-396 [doi]
- Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor SystemsShaobo Liu, Qinru Qiu, Qing Wu. 397-404 [doi]
- A Capacity Co-allocation Configurable Cache for Low Power Embedded SystemsChuanjun Zhang. 405-410 [doi]
- System-Level Energy Modeling for Heterogeneous Reconfigurable Chip MultiprocessorsXiaofang Wang, Sotirios G. Ziavras. 411-416 [doi]
- Improving Power and Data Efficiency with Threaded Memory ModulesFrederick A. Ware, Craig Hampel. 417-424 [doi]
- A New Class of Sequential Circuits with Acyclic Test Generation ComplexityChia Yee Ooi, Hideo Fujiwara. 425-431 [doi]
- Efficient Testing of RF MIMO Transceivers Used in WLAN ApplicationsErkan Acar, Sule Ozev. 432-437 [doi]
- A theory of Error-Rate TestingShideh Shahidi, Sandeep Gupta. 438-445 [doi]
- Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at TestsDong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun. 446-451 [doi]
- Stochastic Dynamic Thermal Management: A Markovian Decision-based ApproachHwisung Jung, Massoud Pedram. 452-457 [doi]
- Design and Implementation of Software Objects in HardwareFu-Chiung Cheng, Hung-Chi Wu. 458-463 [doi]
- An accurate Energy estimation framework for VLIW Processor CoresSourav Roy, Rajat Bhatia, Ashish Mathur. 464-469 [doi]
- Design and Implementation of the TRIPS Primary Memory SystemSimha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler. 470-476 [doi]
- Implementation and Evaluation of On-Chip Network ArchitecturesPaul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger. 477-484 [doi]
- Microarchitecture and Performance Analysis of Godson-2 SMT ProcessorZusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang. 485-490 [doi]
- Patching Processor Design ErrorsSatish Narayanasamy, Bruce Carneal, Brad Calder. 491-498 [doi]
- Choosing an Error Protection Scheme for a Microprocessor s L1 Data CacheNathan Sadler, Daniel Sorin. 499-505 [doi]
- Architectural Support for Run-Time Validation of Control Flow TransferYixin Shi, Sean Dempsey, Gyungho Lee. 506-513 [doi]
- Pesticide: Using SMT Processors to Improve Performance of Pointer Bug DetectionJin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi. 514-521 [doi]
- Trends and Future Directions in Nano Structure Based Computing and FabricationR. Iris Bahar. 522-527 [doi]