External Links

Cite Key

Statistics

  • Reviews: 0
  • Bibliographies: 0

Researchr

Researchr is a web site for finding, collecting, sharing, and reviewing scientific publications, for researchers by researchers.

Sign up for an account to create a profile with publication list, tag and review your related work, and share bibliographies with your co-authors.

26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings

26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings. IEEE, 2008.

Conference: iccd 2008

Abstract

Abstract is missing.

Table of Contents

1-6Fault tolerant Four-State Logic by using Self-Healing Cells
Thomas Panhofer, Werner Friesenbichler, Martin Delvai
7-13Probabilistic error propagation in logic circuits using the Boolean difference calculus
Nasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram
14-20A novel, highly SEU tolerant digital circuit design approach
Rajesh Garg, Sunil P. Khatri
21-26Power-state-aware buffered tree construction
Iris Hui-Ru Jiang, Ming-Hua Wu
27-33A parallel Steiner tree heuristic for macro cell routing
Christian Fobel, Gary Grewal
34-39Configurable rectilinear Steiner tree construction for SoC and nano technologies
Iris Hui-Ru Jiang, Yen-Ting Yu
40-45Improving SAT-based Combinational Equivalence Checking through circuit preprocessing
Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes
46-51Ant Colony Optimization directed program abstraction for software bounded model checking
Xueqi Cheng, Michael S. Hsiao
52-59Propositional approximations for bounded model checking of partial circuit designs
Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew D. T. Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer
60-67Energy-precision tradeoffs in mobile Graphics Processing Units
Jeff Pool, Anselmo Lastra, Montek Singh
68-73Dynamically reconfigurable soft output MIMO detector
Pankaj Bhagawat, Rajballav Dash, Gwan Choi
74-80Applying speculation techniques to implement functional units
Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado
81-86Accelerating search and recognition with a TCAM functional unit
Atif Hashmi, Mikko Lipasti
87-94Improved combined binary/decimal fixed-point multipliers
Brian J. Hickmann, Michael J. Schulte, Mark A. Erle
95-100Architecture implementation of an improved decimal CORDIC method
José Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno
101-106A study of reliability issues in clock distribution networks
Aida Todri, Malgorzata Marek-Sadowska
107-113Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations
Chunchen Liu, Junjie Su, Yiyu Shi
114-119Custom rotary clock router
Vinayak Honkote, Baris Taskin
120-127Safe clocking register assignment in datapath synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
128-133Gate planning during placement for gated clock network
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
134-141Near-optimal oblivious routing on three-dimensional mesh networks
Rohit Sunkam Ramanujam, Bill Lin
142-149Design of application-specific 3D Networks-on-Chip architectures
Shan Yan, Bill Lin
150-155Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic
Ahmad Khonsari, Mohammad R. Aghajani, Arash Tavakkol, Mohammad Sadegh Talebi
156-163A resource efficient content inspection system for next generation Smart NICs
Karthik Sabhanatarajan, Ann Gordon-Ross
164-169Contention-aware application mapping for Network-on-Chip communication architectures
Chen-Ling Chou, Radu Marculescu
170-175Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities
Kaijian Shi
176-181Adaptive SRAM memory for low power and high yield
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham
182-187On-chip high performance signaling using passive compensation
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng
188-193A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters
Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
194-199Characterization and design of sequential circuit elements to combat soft error
Hamed Abrishami, Safar Hatami, Massoud Pedram
200-205Comparative analysis of NBTI effects on low power and high performance flip-flops
Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie
206-211In-field NoC-based SoC testing with distributed test vector storage
Jason D. Lee, Rabi N. Mahapatra
212-218Test-access mechanism optimization for core-based three-dimensional SOCs
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie
219-226Characterization of granularity and redundancy for SRAMs for optimal yield-per-area
Jae Chul Cha, Sandeep K. Gupta
227-233Dynamic test scheduling for analog circuits for improved test quality
Ender Yilmaz, Sule Ozev
234-239Test cost minimization through adaptive test development
Mingjing Chen, Alex Orailoglu
240-247Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA
Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang
248-254A high-performance parallel CAVLC encoder on a fine-grained many-core system
Zhibin Xiao, Bevan Baas
255-259Acceleration of a 3D target tracking algorithm using an application specific instruction set processor
Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois
260-265Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao
266-271Application Specific Instruction set processor specialized for block motion estimation
Marc-Andre Daigneault, J. M. Pierre Langlois, Jean-Pierre David
272-279Prototyping a hybrid main memory using a virtual machine monitor
Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo
280-285Variation-aware thermal characterization and management of multi-core architectures
Eren Kursun, Chen-Yong Cher
286-293Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective
Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai
294-300Analysis and minimization of practical energy in 45nm subthreshold logic circuits
David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
301-306Power-aware soft error hardening via selective voltage scaling
Kai-Chiang Wu, Diana Marculescu
307-314Reversi: Post-silicon validation system for modern microprocessors
Ilya Wagner, Valeria Bertacco
315-320Digital filter synthesis considering multiple adder graphs for a coefficient
Jeong-Ho Han, In-Cheol Park
321-327A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications
Adnan Suleiman, Hani Saleh, Adel Hussein, David Akopian
328-333Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264
Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga
334-339Highly reliable A/D converter using analog voting
Ali Namazi, S. Askari, Mehrdad Nourani
340-347Hierarchical simulation-based verification of Anton, a special-purpose parallel machine
John P. Grossman, John K. Salmon, Richard C. Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw
348-355Post-silicon verification for cache coherence
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
356-362Acquiring an exhaustive, continuous and real-time trace from SoCs
Christian Hochberger, Alexander Weiss
363-370CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin
371-376Exploiting spare resources of in-order SMT processors executing hard real-time threads
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
377-383Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design
Carsten Gremzow
384-389A simple latency tolerant processor
Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song
390-396Low-cost open-page prefetch scheduling in chip multiprocessors
Marius Grannæs, Magnus Jahre, Lasse Natvig
397-403Simulation points for SPEC CPU 2006
Arun A. Nair, Lizy K. John
404-409Synthesis of parallel prefix adders considering switching activities
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
410-415Conversion driven design of binary to mixed radix circuits
Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev
416-421Systematic design of high-radix Montgomery multipliers for RSA processors
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
422-426An improved micro-architecture for function approximation using piecewise quadratic interpolation
Shai Erez, Guy Even
427-431A floating-point fused dot-product unit
Hani Saleh, Earl E. Swartzlander Jr.
432-437Chip level thermal profile estimation using on-chip temperature sensors
Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran
438-443Early stage FPGA interconnect leakage power estimation
Shilpa Bhoj, Dinesh Bhatia
444-449Modeling and analysis of non-rectangular transistors caused by lithographic distortions
Aswin Sreedhar, Sandip Kundu
450-456A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions
Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos
457-462Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield
Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang
463-470Frequency and voltage planning for multi-core processors under thermal constraints
Michael Kadin, Sherief Reda
471-477Understanding performance, power and energy behavior in asymmetric multiprocessors
Nagesh B. Lakshminarayana, Hyesoon Kim
478-485Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
Michael Gschwind
486-490The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks
Reza Sabbaghi-Nadooshan, Mehdi Modarressi, Hamid Sarbazi-Azad
492-497Design and evaluation of an optical CPU-DRAM interconnect
Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew Farrens, Venkatesh Akella
498-505Leveraging speculative architectures for run-time program validation
Juan Carlos Martinez Santos, Yunsi Fei
506-513Bridging the gap between nanomagnetic devices and circuits
Michael T. Niemier, Xiaobo Sharon Hu, Aaron Dingler, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod
514-519Techniques for increasing effective data bandwidth
Christopher Nitta, Matthew Farrens
520-525RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache
Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Kim, Seungryoul Maeng
526-531Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes
Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang
532-537Timing analysis considering IR drop waveforms in power gating designs
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska
538-543A dynamic accuracy-refinement approach to timing-driven technology mapping
Sz-Cheng Huang, Jie-Hong Roland Jiang
544-550Modeling and reduction of complex timing constraints in high performance digital circuits
Veerapaneni Nagbhushan, C. Y. Roger Chen
551-556SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement
Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi
557-562Is there always performance overhead for regular fabric?
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
563-569Adaptive techniques for leakage power management in L2 cache peripheral circuits
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot
570-576Energy-aware opcode design
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
577-582Making register file resistant to power analysis attacks
Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhijie Jerry Shi
583-590Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads
Shrirang M. Yardi, Michael S. Hsiao
591-598Suitable cache organizations for a novel biomedical implant processor
Christos Strydis
599-604Issue system protection mechanisms
Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera
605-611Power switch characterization for fine-grained dynamic voltage scaling
Liang Di, Mateja Putic, John Lach, Benton H. Calhoun
612-617A fine-grain dynamic sleep control scheme in MIPS R3000
Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
618-625Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW
Hao Xu, Ranga Vemuri, Wen-Ben Jone
626-632Energy-delay tradeoffs in 32-bit static shifter designs
Steven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil
633-639Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems
Baoxian Zhao, Hakan Aydin, Dakai Zhu
640-645Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits
Feng Shi
646-651Router and cell library co-development for improving redundant via insertion at pins
Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin
652-657ECO-Map: Technology remapping for post-mask ECO using simulated annealing
Nilesh A. Modi, Malgorzata Marek-Sadowska
658-663Global bus route optimization with application to microarchitectural design exploration
Dae-Hyun Kim, Sung Kyu Lim
664-670Fast arbiters for on-chip network switches
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos
671-678Re-examining cache replacement policies
Jason Zebchuk, Srihari Makineni, Donald Newell
679-684Two dimensional highly associative level-two cache design
Chuanjun Zhang, Bing Xue
685-692Exploiting producer patterns and L2 cache for timely dependence-based prefetching
Chungsoo Lim, Gregory T. Byrd
693-698Ring data location prediction scheme for Non-Uniform Cache Architectures
Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin
699-706ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits
Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum
runs on