Table of Contents

• 3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access timeIshan G. Thakkar, Sudeep Pasricha. 1-7 [doi]
• The Blacklisting Memory Scheduler: Achieving high performance and fairness at low costLavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu. 8-15 [doi]
• Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memoryMengying Zhao, Liang Shi, Chengmo Yang, Chun Jason Xue. 16-21 [doi]
• ProactiveDRAM: A DRAM-initiated retention management schemeJue Wang, Xiangyu Dong, Yuan Xie 0001. 22-27 [doi]
• HAP: Hybrid-memory-Aware Partition in shared Last-Level CacheWei Wei, Dejun Jiang, Jin Xiong, Mingyu Chen. 28-35 [doi]
• REEM: Failure/non-failure region estimation method for SRAM yield analysisManish Rana, Ramon Canal. 36-41 [doi]
• Efficient design of FIR filters using hybrid multiple constant multiplications on FPGALevent Aksoy, Paulo F. Flores, José C. Monteiro. 42-47 [doi]
• A low-power accuracy-configurable floating point multiplierHang Zhang, Wei Zhang, John Lach. 48-54 [doi]
• An area-efficient Ternary CAM design using floating gate transistorsViacheslav V. Fedorov, Monther Abusultan, Sunil P. Khatri. 55-60 [doi]
• Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline exampleAndreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel. 61-67 [doi]
• iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data cachesShrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio. 68-74 [doi]
• Multi-accelerator system development with the ShrinkFit acceleration frameworkMichael J. Lyons, Gu-Yeon Wei, David Brooks. 75-82 [doi]
• Ternary cache: Three-valued MLC STT-RAM cachesSeokin Hong, Jongmin Lee 0002, Soontae Kim. 83-89 [doi]
• Timing error masking by exploiting operand value locality in SIMD architectureJaehyeong Sim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim. 90-96 [doi]
• Accurate prediction of detailed routing congestion using supervised data learningZhongdong Qi, Yici Cai, Qiang Zhou. 97-103 [doi]
• SFFMap: Set-First Fill mapping for an energy efficient pipelined data cachePritam Majumder, T. Venkata Kalyan, Madhu Mutyam. 104-109 [doi]
• ReMAP: Reuse and memory access cost aware eviction policy for last level cache managementAkhil Arunkumar, Carole-Jean Wu. 110-117 [doi]
• Dynamic associative caches: Reducing dynamic energy of first level cachesKarthikeyan Dayalan, Meltem Ozsoy, Dmitry V. Ponomarev. 118-124 [doi]
• Increasing cache capacity via critical-words-only cacheCheng-Chieh Huang, Vijay Nagarajan. 125-132 [doi]
• Optimizing MLC-based STT-RAM caches by dynamic block size reconfigurationJianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li. 133-138 [doi]
• ITRS 2.0: Toward a re-framing of the Semiconductor Technology RoadmapJuan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath. 139-146 [doi]
• More Moore landscape for system readiness - ITRS2.0 requirementsMustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, SungGeun Kim, Gerhard Klimeck, Chorng-Ping Chang, Charles Cheung, Yuzo Fukuzaki. 147-152 [doi]
• The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmapWei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto. 153-160 [doi]
• Updates of the ITRS design cost and power modelsGary Smith. 161-165 [doi]
• A lightweight and open-source framework for the lifetime estimation of multicore systemsCristiana Bolchini, Matteo Carminati, Marco Gribaudo, Antonio Miele. 166-172 [doi]
• Advanced modes in AES: Are they safe from power analysis based side channel attacks?Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran. 173-180 [doi]
• Built-in self-test for interposer-based 2.5D ICsRan Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. 181-188 [doi]
• An optimized diagnostic procedure for pre-bond TSV defectsBei Zhang, Vishwani D. Agrawal. 189-194 [doi]
• Equivalence verification for NULL Convention Logic (NCL) circuitsVidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith. 195-201 [doi]
• Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systemsCongming Gao, Liang Shi, Kaijie Wu, Chun Jason Xue, Edwin Hsing-Mean Sha. 202-207 [doi]
• Write-aware random page initialization for non-volatile memory systemsFei Xia, Dejun Jiang, Jin Xiong, Ninghui Sun. 208-215 [doi]
• Loose-Ordering Consistency for persistent memoryYouyou Lu, Jiwu Shu, Long Sun, Onur Mutlu. 216-223 [doi]
• Design space exploration of an NVM-based memory hierarchySeungjae Baek, Daeyeon Son, Dongwoo Kang, Jongmoo Choi, Sangyeun Cho. 224-229 [doi]
• Timing characterization of clock buffers for clock tree synthesisCan Sitik, Scott Lerner, Baris Taskin. 230-236 [doi]
• Improving power delivery network design by practical methodologiesChia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai. 237-242 [doi]
• Chip clustering with mutual information on multiple clock tests and its application to yield tuningJiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou. 243-248 [doi]
• Simultaneous EUV flare- and CMP-aware placementChi-Yuan Liu, Yao-Wen Chang. 249-255 [doi]
• Modeling and analysis of Phase Change Materials for efficient thermal managementFulya Kaplan, Charlie De Vivero, Samuel Howes, Manish Arora, Houman Homayoun, Wayne Burleson, Dean M. Tullsen, Ayse Kivilcim Coskun. 256-263 [doi]
• Improving multilevel PCM reliability through age-aware reading and writing strategiesChen Liu, Chengmo Yang. 264-269 [doi]
• BarTLB: Barren page resistant TLB for managed runtime languagesXin Tong, Andreas Moshovos. 270-277 [doi]
• A Thread-Aware Adaptive Data PrefetcherJiyang Yu, Peng Liu 0016. 278-285 [doi]
• Dynamic front-end sharing in graphics processing unitsTao Zhang, Xiaoyao Liang. 286-291 [doi]
• Leveraging dynamic slicing to enhance indirect branch predictionWalid J. Ghandour, Nadine J. Ghandour. 292-299 [doi]
• DFM is dead - Long live DFMRobert C. Aitken, David Pietromonaco, Brian Cline. 300-307 [doi]
• Pattern-restricted design at 10nm and beyondRani S. Ghaida, Yasmine Badr, Puneet Gupta. 308-310 [doi]
• Improved signoff methodology with tightened BEOL cornersTuck Boon Chan, Sorin Dobre, Andrew B. Kahng. 311-316 [doi]
• Accelerating divergent applications on SIMD architectures using neural networksBeayna Grigorian, Glenn Reinman. 317-323 [doi]
• Power-capped DVFS and thread allocation with ANN models on modern NUMA systemsSatoshi Imamura, Hiroshi Sasaki, Koji Inoue, Dimitrios S. Nikolopoulos. 324-331 [doi]
• QoS management on heterogeneous architecture for parallel applicationsYing Zhang, Li Zhao, Ramesh Illikkal, Ravi Iyer, Andrew Herdrich, Lu Peng. 332-339 [doi]
• Software pipelining of dataflow programs with dynamic constructs on multi-core processorYogesh Murarka, Pankaj Shailendra Gode, Sirish Kumar Pasupuleti, Soma Kohli. 340-347 [doi]
• Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodesDaming Zhang, Shuangchen Li, Ang Li, Yongpan Liu, Xiaobo Sharon Hu, Huazhong Yang. 348-354 [doi]
• Boolean circuit design using emerging tunneling devicesBehnam Sedighi, Joseph J. Nahas, Michael T. Niemier, Xiaobo Sharon Hu. 355-360 [doi]
• Compact and accurate stochastic circuits with shared random number sourcesHideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue. 361-366 [doi]
• Analyzing and controlling accuracy in stochastic circuitsTe-Hsuan Chen, John P. Hayes. 367-373 [doi]
• Low write-energy STT-MRAMs using FinFET-based access transistorsAlireza Shafaei, Yanzhi Wang, Massoud Pedram. 374-379 [doi]
• Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technologyQing Xie, Yanzhi Wang, Shuang Chen, Massoud Pedram. 380-385 [doi]
• The heterogeneous block architectureChris Fallin, Chris Wilkerson, Onur Mutlu. 386-393 [doi]
• An asynchronous Network-on-Chip router with low standby powerAmr Elshennawy, Sunil P. Khatri. 394-399 [doi]
• NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle coresXiang Pan, Radu Teodorescu. 400-407 [doi]
• Design-effort alloy: Boosting a highly tuned primary core with untuned alternate coresElliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg. 408-415 [doi]
• Energy efficiency improvement of renamed trace cache through the reduction of dependent path lengthRyota Shioya, Hideki Ando. 416-423 [doi]
• Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-ChipsCostas Iordanou, Vassos Soteriou, Konstantinos Aisopos. 424-431 [doi]
• An energy efficient column-major backend for FPGA SpMV acceleratorsYaman Umuroglu, Magnus Jahre. 432-439 [doi]
• Fair share: Allocation of GPU resources for both performance and fairnessPaula Aguilera, Katherine Morrow, Nam Sung Kim. 440-447 [doi]
• Dynamic variability management in mobile multicore processors under lifetime constraintsPietro Mercati, Francesco Paterna, Andrea Bartolini, Luca Benini, Tajana Simunic Rosing. 448-455 [doi]
• Design space exploration of multiple loops on FPGAs using high level synthesisGuanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra, Smaïl Niar. 456-463 [doi]
• Storage-allocation to sequential structures in High-Level Synthesis-assisted prototypingVinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar. 464-469 [doi]
• HW/SW partitioning for region-based dynamic partial reconfigurable FPGAsYuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk. 470-476 [doi]
• Power supply and consumption co-optimization of portable embedded systems with hybrid power supplyXue Lin, Yanzhi Wang, Naehyuck Chang, Massoud Pedram. 477-482 [doi]
• Automated generation of battery aging models from datasheetsMassimo Petricca, Donghwa Shin, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino. 483-488 [doi]
• Optimal variable ordering in ZBDD-based path representations for directed acyclic graphsStelios N. Neophytou, Maria K. Michael. 489-492 [doi]
• Hybrid modeling attacks on current-based PUFsRaghavan Kumar, Wayne P. Burleson. 493-496 [doi]
• CoolBudget: Data center power budgeting with workload and cooling asymmetry awarenessOzan Tuncer, Kalyan Vaidyanathan, Kenny C. Gross, Ayse Kivilcim Coskun. 497-500 [doi]
• Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systemsSiddharth Advani, Nandhini Chandramoorthy, Karthik Swaminathan, Kevin M. Irick, Yong Cheol Peter Cho, Jack Sampson, Vijaykrishnan Narayanan. 501-504 [doi]
• Exploiting natural redundancy in visual informationChris S. Lee, Kevin M. Irick, Jack Sampson, Chuanjun Zhang, Vijaykrishnan Narayanan. 505-508 [doi]
• Dark silicon aware power management for manycore systems under dynamic workloadsMohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Awet Yemane Weldezion, Pasi Liljeberg, Juha Plosila, Axel Jantsch, Hannu Tenhunen. 509-512 [doi]
• Cache design for mixed criticality real-time systemsN. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones. 513-516 [doi]
• Static thread mapping for NoCs via binary instrumentation tracesGiordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead, Ankit More. 517-520 [doi]
• ScalaHDL: Express and test hardware designs in a Scala DSLYao Li, Antonio Roldao Lopes, Zhouyun Xu, Zhengwei Qi, Haibing Guan. 521-524 [doi]
• PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCsNishit Ashok Kapadia, Sudeep Pasricha. 525-528 [doi]