Table of Contents

• A low power variable GBW opamp from 60MHz to 2GHz for multi-standard receiversAytac Atac, Christian Harder, Ralf Wunderlich, Stefan Heinen. 1-4 [doi]
• Low-voltage CMOS current feedback amplifierVictoria Pisani, Ivan Grech, Owen Casha, Edward Gatt. 5-8 [doi]
• Optimization based on surrogate modeling for analog integrated circuitsFiras Yengui, Lioula Labrak, Patrice Russo, Felipe Frantz, Nacer Abouchi. 9-12 [doi]
• Web-based analog design using tradeoff chartsA. Hamza, A. Philip, M. Ali, M. Dessouky, M. Kassem. 13-16 [doi]
• Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversionAthanasios Dimakos, Matthias Bucher, Rupendra Kumar Sharma, Ilias Chlis. 17-20 [doi]
• Evaluating the influence of the bit error rate on the information of neural spike signalsChristoph Bulach, Ulrich Bihr, Maurits Ortmanns. 21-24 [doi]
• Towards an optimized wearable neuromodulation device for urinary incontinenceA. N. Shiraz, Andreas Demosthenous, Anne Vanhoestenberghe. 25-28 [doi]
• Towards a closed-loop transmitter system with integrated class-D amplifier for coupling-insensitive powering of implantsVirgilio Valente, Clemens Eder, Andreas Demosthenous, Nick Donaldson. 29-32 [doi]
• Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoringFlorent Dupont, Cyril Condemine, Jean-François Beche, Marc Belleville. 33-36 [doi]
• Selection of wavelet-bands for neural network discrimination of Parkinsonian tremor from essential tremorAbdulnasir Hossen. 37-40 [doi]
• Hardware-efficient matrix inversion algorithm for complex adaptive systemsAlfredo Rosado, Taras Iakymchuk, Manuel Bataller, Marek Wegrzyn. 41-44 [doi]
• Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noiseTaras Iakymchuk, Alfredo Rosado, Emilio Soria-Olivas, Manuel Bataller. 45-48 [doi]
• RADS converter: An approach to Analog to Information conversionSalvador Javier Haboba, Riccardo Rovatti, Gianluca Setti. 49-52 [doi]
• High-speed compressed sensing reconstruction on FPGA using OMP and AMPLin Bai, Patrick Maechler, Michael Muehlberghuber, Hubert Kaeslin. 53-56 [doi]
• A linearity enhancement technique and its application to CMOS wideband low-noise amplifiersAmir Hossein Masnadi Shirazi, Hooman Rashtian, Shahriar Mirabbasi. 57-60 [doi]
• A 7GHz wideband self-correcting quadrature VCOTomoyuki Arai, Ali Hajimiri. 61-64 [doi]
• Design methodology and integration of a 1.8GHz outphasing power amplifier for mobile terminalsOmid Talebi Amiri, Adil Koukab. 65-68 [doi]
• 4.0-5.5 GHz tunable power splitter RFIC using active inductorsYou Zheng, Carlos E. Saavedra. 69-72 [doi]
• Design of ADPLL system for WiMAX applications in 40-nm CMOSWenlong Jiang, Armin Tavakol, Popong Effendrik, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski. 73-76 [doi]
• A soft IP core generating SoCs for the efficient stochastic simulation of large Biomolecular Networks using FPGAsOrsalia Georgia Hazapis, Evangelos Logaras, Elias S. Manolakos. 77-80 [doi]
• Signal processing for deep-sea observatories with reconfigurable hardwareKonstantinos Manolopoulos, A. Belias, Georgios Georgis, Dionysios I. Reisis, E. G. Anasontzis. 81-84 [doi]
• FPGA-based path-planning of high mobility rover for future planetary missionsGeorge Lentaris, Dionysios Diamantopoulos, G. Stamoulias, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez. 85-88 [doi]
• Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAsAhmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras. 89-92 [doi]
• FPGA based cellular automata for environmental modelingIoannis Vourkas, Georgios Ch. Sirakoulis. 93-96 [doi]
• A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillatorKeishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa. 97-100 [doi]
• Compact class-AB follower for wideband closed loop line driversDavid Gascon, Andreu Sanuy, Javier J. Sieiro. 101-104 [doi]
• A low-distortion switched-source-follower track-and-hold circuitAkinori Moriyama, Satoshi Taniyama, Takao Waho. 105-108 [doi]
• A 2.5-GS/s 62dB THD SiGe Track-and-Hold Amplifier with feedthrough cancellation techniqueDamiano Cascella, Francesco Cannone, Gianfranco Avitabile, Giuseppe Coviello. 109-112 [doi]
• A CMOS track-and-hold circuit with beyond 30 GHz input bandwidthBehnam Sedighi, Anh T. Huynh, Efstratios Skafidas. 113-116 [doi]
• All-Digital A/D converter TAD for sensor interface over wide temperature rangesTakamoto Watanabe, Hirofumi Isomura, Tomohito Terasawa. 117-120 [doi]
• A readout circuit implementation to reduce the flicker noise in MEMS electrothermal sensorsA. Mohammadi, Mehmet R. Yuce, S. O. Reza Moheimani. 121-124 [doi]
• In Pixel Implementation of autoadaptative integration timeHassan Abbass, Hawraa Amhaz, Gilles Sicard, David Alleysson. 125-128 [doi]
• Design and implementation of a neurocomputing ASIP for environmental monitoring in WSNJochen Rust, Steffen Paul. 129-132 [doi]
• A system-proof-of-concept for remote measurement applicationsMarko Mailand, Stefan Getzlaff, Andrew David Dehennis. 133-136 [doi]
• FPGA implementation of simple digital signal processorMarko Butorac, Mladen Vucic. 137-140 [doi]
• Improving palmprint identification by combining multiple classifiers and using gabor filterAbdallah Meraoumia, Salim Chitroub, Ahmed Bouridane. 141-144 [doi]
• Protein alignment HW/SW optimizationsGianvito Urgese, Mariagrazia Graziano, Marco Vacca, Muhammad Awais, Stefano Frache, Maurizio Zamboni. 145-148 [doi]
• Parallel scaling-free and area-time efficient CORDIC algorithmMatteo Causo, Ting An, Lirida Alves de Barros Naviner. 149-152 [doi]
• A VLSI architecture for multiple antenna eigenvalue-based spectrum sensingSeyede Mahya Safavi, Mahdi Shabany. 153-156 [doi]
• A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18µm CMOSHossein Jalili, Ali Fotowat Ahmady, Mahta Jenabi. 157-160 [doi]
• A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applicationsKaushik Ghosal, Tejasvi Anand, Vikram Chaturvedi, Bharadwaj Amrutur. 161-164 [doi]
• A 20 Mb/s 0.084 nJ/bit ISM-band transmitter dedicated to medical sensor networksArash Moradi, Mohamad Sawan. 165-168 [doi]
• Analysis and characterization of mismatches in outphasing transmitterShailesh Kulkarni, Dixian Zhao, Patrick Reynaert. 169-172 [doi]
• A 60GHz class F-E power VCO with vector-modulator feedback in 65nm CMOS technologySophie Drean, N. Martin, Nathalie Deltimple, Eric Kerherve, Baudouin Martineau, Didier Belot. 173-176 [doi]
• A low-power CMOS RF power detectorSiraporn Sakphrom, Apinunt Thanachayanont. 177-180 [doi]
• Millimeter-wave high-Q active inductor in 65nm CMOSDomenico Pepe, Domenico Zito. 181-184 [doi]
• Windowed phase comparator for an 80Gbit/s CDRQuentin Beraud-Sudreau, Olivier Mazouffre, Michel Pignol, L. Baguena, Claude Neveu, Jean-Baptiste Begueret, Thierry Taris. 185-188 [doi]
• A novel multi-step C-2C DAC architectureMazyar Abedinkhan, Amir Masoud Sodagar, Reza Mohammadi, Payman Adl. 189-192 [doi]
• A CMOS 0.13µm low power front-end for GEM detectorsAndrea Costantini, Alessandro Pezzotta, Andrea Baschirotto, Marcello De Matteis, Stefano D'Amico, F. Murtas, G. Gorini. 193-196 [doi]
• All-digital A/D converter TAD for high-resolution and low-power sensor/RF interfaceTakamoto Watanabe, Tomohito Terasawa. 197-200 [doi]
• Temperature considerations on Hall Effect sensors current-related sensitivity behaviourMaria-Alexandra Paun, Jean-Michel Sallese, Maher Kayal. 201-204 [doi]
• A tri-mode event-based vision sensor with an embedded wireless transmitterJuan Antonio Leñero-Bardallo, Wei Tang, Dongsoo Kim, Joon Hyuk Park, Eugenio Culurciello. 205-208 [doi]
• Improved high precision optical angle measurement system with no interference of light gradients and mismatchJürgen Oehm, Christian Koch, Ivan Stoychev, Andreas Gornik. 209-212 [doi]
• A 10Gb/s inductorless push pull current mirror transimpedance amplifierMohammed Hassan, Horst Zimmermann. 213-216 [doi]
• Performance evaluation for FPGA-based processing of tree-like structuresValery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson. 217-220 [doi]
• FPGA implementation of very high radix square root with prescalingAlexandru Amaricai, Oana Boncalo. 221-224 [doi]
• Performance evaluation of RAM-based implementation of Finite State Machines in FPGAsRaouf Senhadji Navarro, Ignacio Garcia-Vargas, Jose Luis Guisado. 225-228 [doi]
• FPGA-based autonomous parking of a car-like robot using Fuzzy Logic ControlNeil Scicluna, Edward Gatt, Owen Casha, Ivan Grech, Joseph Micallef. 229-232 [doi]
• A generic FPGA emulation frameworkFernando Gehm Moraes, Matheus T. Moreira, C. Lucas, D. Correa, Douglas de O. Cardoso, M. Magnaguagno, Guilherme M. Castilhos, Ney Laert Vilar Calazans. 233-236 [doi]
• Design of a 80 Gbit/s SiGe BiCMOS fully differential input buffer for serial electrical communicationTimothy De Keulenaer, Yu Ban, Zhisheng Li, Johan Bauwelinck. 237-239 [doi]
• A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driverH. W. Marar, K. Abugharbieh, A.-K. Al-Tamimi. 240-243 [doi]
• Accessible approach to wideband matchingAnu Lehtovuori, Risto Valkonen, Martti Valtonen. 244-247 [doi]
• A generalized graphical model to specify A/D resolution from receiver front-endShenjie Wang, Catherine Dehollain. 248-251 [doi]
• Lumped-element-based single/dual-passband analog filters using signal-interference principlesRaul Loeches-Sanchez, Roberto Gómez-Garcia, Bernard Jarry, Julien Lintignat, Bruno Barelaud. 252-255 [doi]
• Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filtersAntonio Jose Ginés, Alberto Villegas, Eduardo J. Peralías, Adoración Rueda. 256-259 [doi]
• rd-order Active-Gm-RC 250MHz-bandwidth analog filter based on power-stability optimizationMarcello De Matteis, Stefano D'Amico, Andrea Costantini, Alessandro Pezzotta, Andrea Baschirotto. 260-263 [doi]
• Dynamic range improvement of new leap-frog filter using numerical optimizationDrazen Jurisic, Neven Mijat, George S. Moschytz. 264-267 [doi]
• A fourth order CMOS band pass filter for PIR sensorsGinés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, J. Zapata-Perez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, F. Fernandez-Luque, Juan M. Carrillo, Miguel Angel Domínguez. 268-271 [doi]
• Accurate estimation of analog test metrics with extreme circuitsKamel Beznia, Ahcène Bounceur, Louay Abdallah, Ke Huang, Salvador Mir, Reinhardt Euler. 272-275 [doi]
• Single pass temperature calibration of the ASIC on a general purpose ATEJanez Trontelj, Blaz Smid, Janez Trontelj. 276-279 [doi]
• A template for the construction of efficient checkers with full verification guaranteesLeandro S. Freitas, Gabriel A. G. Andrade, Luiz C. V. dos Santos. 280-283 [doi]
• A formal framework for testing with assertion checkers in mixed-signal simulationLaurence Pierre. 284-287 [doi]
• Design and characterization of a QLUT in a standard CMOS processDiogo Brito, Jorge Fernandes, Paulo F. Flores, José C. Monteiro. 288-291 [doi]
• Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexitySeyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan. 292-295 [doi]
• Maximum delay variation temperature-aware standard cell designMarc Pons, Jean-Luc Nagel, Christian Piguet. 296-299 [doi]
• A low complexity architecture for the cell search applied to the LTE systemsAmeneh Golnari, Golnoosh Sharifan, Yalda Amini, Mahdi Shabany. 300-303 [doi]
• Digitizing The Yuan Tseh Lee Array for Microwave Background Anisotropy by 5Gsps ADC boardsHomin Jiang, H. Liu, K. Guzzino, D. Kubo, Chao-Te Li, R. Chang. 304-307 [doi]
• PMEPR reduction for OFCDM using SLM and PTSS. M. Z. S. Shah, A. W. Umrani, A. A. Memon, S. M. Z. A. Shah. 308-311 [doi]
• Adaptive slope and threshold companding technique for PAPR reduction in OFDM systemsVivek Yenamandra, Feiran Lei, Saleh Al-Araji, Nazar Ali, Mohammed Ismail. 312-315 [doi]
• Selective channelization on an SDR platform for LTE-a carrier aggregationI. Diaz, Rodolfo Torrea Duran, Sofie Pollin, Liesbet Van der Perre, Viktor Öwall. 316-319 [doi]
• A novel implementation of sequential output based parallel processing - orthogonal wavelet division multiplexing for DAS on SDR platformChinmaya Mahapatra, A. Ramakrishnan, Thanos Stouraitis, Victor C. M. Leung. 320-323 [doi]
• Mixed signal SIMD cellular processor array vision chip operating at 30, 000 fpsStephen J. Carey, David Robert Wallace Barr, Bin Wang, Alexey Lopich, Piotr Dudek. 324-327 [doi]
• Bottom-up visual attention model based on FPGAFrancisco Barranco, Javier Díaz, Begoña del Pino, Eduardo Ros. 328-331 [doi]
• CMOS SPADs selection, modeling and characterization towards image sensors implementationM. M. Garcia, O. G. Vinuesa, Rocío del Río Fernández, B. P. Verdu, Ángel Rodríguez-Vázquez. 332-335 [doi]
• Embedded low-power low-cost Camera Sensor based on FPGA and its applications in mobile robotsJordi Albo-Canals, S. Ortega, S. Perdices, A. Badalov, Xavier Vilasís-Cardona. 336-339 [doi]
• High Dynamic Range image sensor with self adapting integration time in 3D technologyFadoua Guezzi Messaoud, Antoine Dupret, Arnaud Peizerat, Yves Blanchard. 340-343 [doi]
• A/D conversion of the battery voltage in advanced CMOS technologiesMarco Zamprogno, Alberto Minuti, Francesca Girardi, Germano Nicollini. 344-347 [doi]
• On the design of a 2-2-0 MASH delta-sigma-pipeline modulatorReza Mohammadi, Hossein Shamsi, Mazyar Abedinkhan. 348-351 [doi]
• Analysis of VCO based noise shaping ADCs linearized by PWM modulationLuis Hernández, Enrique Prefasi, Susanna Patón, Pieter Rombouts. 352-355 [doi]
• Design of an undersampled BP ΣΔ modulator using LC and time-interleaved resonatorsNicolas Beilleau, V. Bourguet, F. R. de Sousa. 356-359 [doi]
• Incremental-ΣΔ-ADCs with dynamic conversion length adaptionJohannes Uhlig, René Schüffny. 360-363 [doi]
• Interpolation filter design for hearing-aid audio class-D output stage applicationPeter Pracný, Pere Llimos Muntal, Erik Bruun. 364-367 [doi]
• Dual data pulse width modulator for wireless Simultaneous Measurement of Redox Potential and Temperature using a Single RFID ChipBoram Kim, Kazuo Nakazato. 368-371 [doi]
• The wireless system for EGG signal acquisitionDariusz Komorowski, Stanislaw Pietraszek, Damian Grzechca. 372-375 [doi]
• A high dynamic range wideband CMOS phase angle detector for bioimpedance spectroscopyJosé L. Ausín, J. Ramos, J. Francisco Duque-Carrillo, Guido Torelli. 376-379 [doi]
• Hardware-in-the-loop simulations of circuit architectures for the computation of exact and approximate explicit MPC control functionsAlberto Oliveri, Marco Storace. 380-383 [doi]
• VLSI Implementation of digital frequency sensors as hardware countermeasureRaúl Jiménez, Guillermo Feria, Juan Antonio Gómez Galán, Fernando Gómez-Bravo, M. Sanchez. 384-387 [doi]
• ASIC-in-the-loop methodology for verification of piecewise affine controllersMacarena C. Martinez-Rodriguez, Piedad Brox, J. Castro, Erica Tena, Antonio J. Acosta, Iluminada Baturone. 388-391 [doi]
• Reducing bit flipping problems in SRAM physical unclonable functions for chip identificationSusana Eiroa, Javier Castro-Ramirez, Macarena Cristina Martinez-Rodriguez, Erica Tena, Piedad Brox, Iluminada Baturone. 392-395 [doi]
• Low energy high speed reed-solomon decoder using two parallel modified evaluator Inversionless Berlekamp-MasseyHazem A. Ahmed, Hamed Salah, Tallal Elshabrawy, Hossam A. H. Fahmy. 396-399 [doi]
• High speed low complexity radix-16 Max-Log-MAP SISO decoderOscar Sanchez, C. Jegoy, Michel Jézéquel, Yannick Saouter. 400-403 [doi]
• High-throughput FPGA-based emulator for structured LDPC codesFabian Angarita, Vicente Torres-Carot, Asuncion Perez-Pascual, Javier Valls. 404-407 [doi]
• Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGAVicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls. 408-411 [doi]
• Decoder for an enhanced serial generalized bit flipping algorithmFrancisco Garcia-Herrero, María José Canet, Javier Valls. 412-415 [doi]
• nd-order low-pass multibit ΣΔ modulatorsAndrea Barbieri, Sergio Pernici, Germano Nicollini. 416-419 [doi]
• Performance tuning of multi-bit continuous time ΣΔ-modulators using a switched system modelChristoph Zorn, Timon Brückner, Maurits Ortmanns, Wolfgang Mathis. 420-423 [doi]
• Analysis of exponentially decaying pulse shape DACs in continuous-time sigma-delta modulatorsSha Tao, Julian Garcia, Saul Rodriguez Duenas, Ana Rusu. 424-427 [doi]
• Joint estimation of filter nonidealities in continuous-time sigma-delta modulators by using an unscented Kalman filterMatthias Lorenz, Michael Maurer, Yiannos Manoli, Maurits Ortmanns. 428-431 [doi]
• Discrete-time simulation of arbitrary digital/analog converter waveforms in continuous-time sigma-delta modulatorsTimon Brückner, Martin Kiebler, Christoph Zorn, Wolfgang Mathis, Maurits Ortmanns. 432-435 [doi]
• CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysisMajid Zamani, Clemens Eder, Andreas Demosthenous. 436-439 [doi]
• Peak power estimation using activity measured on emulatorChristian Berthet, Philippe Georgelin, Janvier Ntyame, Mathieu Raffin. 440-443 [doi]
• A dual threshold voltage technique for glitch minimizationMariem Slimani, Philippe Matherat, Yves Mathieu. 444-447 [doi]
• A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOSS. M. Yasser Sherazi, Peter Nilsson, Henrik Sjöland, Joachim Neves Rodrigues. 448-451 [doi]
• Low-power two's-complement multiplication based on selective activationPanagiotis Sakellariou, Vassilis Paliouras. 452-455 [doi]
• Efficient optimization methodology for CT functions based on a modified bayesian kriging approachCatalin-Adrian Tugui, R. Benassi, S. Apostol, Philippe Bénabès. 456-459 [doi]
• An efficient solution space for floorplan of 3D-LSIHiroshi Tezuka, Kunihiro Fujiyoshi. 460-463 [doi]
• Fast floorplanning for fixed-outline and nonrectangular regionsMohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske. 464-467 [doi]
• Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimizationVincius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann. 468-471 [doi]
• Finding the Hamiltonian circuits in an undirected graph using the mesh-links incidenceCristian E. Onete, Maria Cristina C. Onete. 472-475 [doi]
• Improved Linearization of a high power amplifier to reduce spectral distortions near the saturation areaMathilde Brandon, Myriam Ariaudo, Sylvain Traverso, J. Bouvier, Jean-Luc Gautier, Inbar Fijalkow. 476-479 [doi]
• Bifurcation diagrams in MOS-NDR frequency divider circuitsJuan Núñez, Maria J. Avedillo, José M. Quintana. 480-483 [doi]
• Nonlinear harmonic analysis of multistage amplifiersAntonio Buonomo, Alessandro Lo Schiavo. 484-487 [doi]
• A "divide-by-odd number" direct injection CMOS LC injection-locked frequency dividerMasfandyar Asfandyar Awan, Malik Summair Asghar, Michael Peter Kennedy. 488-491 [doi]
• Design for linearizability of GaN based multi-carrier Doherty power amplifier through bias optimizationOualid Hammi, Sung-Chan Jung, Fadhel M. Ghannouchi. 492-495 [doi]
• A 4-bit 1.5GSps 4.2mW comparator-based binary search ADC in 90nmTaimur Gibran Rabuske, Fabio Gibran Rabuske, Jorge R. Fernandes, Cesar Ramos Rodrigues. 496-499 [doi]
• A 749nW 1MSps 8-bit SAR ADC at 0.5V employing boosted switchesTaimur Gibran Rabuske, Jorge R. Fernandes, Saeid Nooshabadi, Cesar Ramos Rodrigues, Fabio Gibran Rabuske. 500-503 [doi]
• A low-power fully differential cyclic 9-bit ADCNiko Bako, Adrijan Baric. 504-507 [doi]
• Design of hybrid resistive-capacitive DAC for SAR A/D convertersBehnam Sedighi, Anh T. Huynh, Efstratios Skafidas, Daniel Micusik. 508-511 [doi]
• A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signalsKisu Kim, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano. 512-515 [doi]
• An ultra-low power li-ion battery charger for micro-power solar energy harvesting applicationsNaser Khosro Pour, Stefano Facchin, François Krummenacher, Maher Kayal. 516-519 [doi]
• A passive CMOS rectifier with leakage current control for medical implantsM. A. Ghanad, Catherine Dehollain. 520-523 [doi]
• Design comparison of low-power rectifiers dedicated to RF energy harvestingD. Karolak, Thierry Taris, Yann Deval, Jean-Baptiste Begueret, Andre A. Mariano. 524-527 [doi]
• A process-compatible passive RFID tag's digital design for subthreshold operationWeiwei Shi, Oliver Chiu-sing Choy. 528-531 [doi]
• Design and analysis of multi-core homogeneous systems for energy harvesting applicationsMeeta Srivastav, Leyla Nazhandali. 532-535 [doi]
• On AOP techniques for C++-based HW/SW component implementationTiago Rogério Mück, Antônio Augusto Fröhlich. 536-539 [doi]
• An RTL method for hiding clock domain crossing latencyGhaith Tarawneh, Alex Yakovlev. 540-543 [doi]
• Enhancing performance of MPSoCs through distributed resource managementMarcelo Mandelli, Guilherme M. Castilhos, Fernando Gehm Moraes. 544-547 [doi]
• Evaluation of adaptive management techniques in NoC-Based MPSoCsFernando Gehm Moraes, Everton Alceu Carara, Marcelo Ruaro, Guilherme A. Madalozzo. 548-551 [doi]
• A redundant wire addition method for Patchable AcceleratorMasayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi, Shigeru Yamashita. 552-555 [doi]
• Hybrid multiple constant multiplication for FPGAsMartin Kumm, Peter Zipf. 556-559 [doi]
• Scene-based noise reduction on a smart cameraFaouzi Hamdi, Tomasz Toczek, Barthélémy Heyrman, Dominique Ginhac. 560-563 [doi]
• Dynamic tree-depth adjustment for low power HEVC encodersGuilherme Corrêa, Pedro Assuncao, Luís Alberto da Silva Cruz, Luciano Volcan Agostini. 564-567 [doi]
• Fast HEVC intra mode decision based on dominant edge evaluation and tree structure dependenciesThaísa Leal da Silva, Luís Alberto da Silva Cruz, Luciano Volcan Agostini. 568-571 [doi]
• A high quality hardware friendly motion estimation algorithm focusing in HD videosPargles Dall'Oglio, Cassio Cristani, Marcelo Schiavon Porto, Luciano Volcan Agostini. 572-575 [doi]
• A telemetry operated vestibular prosthesisDominik Cirmirakis, Dai Jiang, Andreas Demosthenous, Nick Donaldson, Timothy Perkins. 576-578 [doi]
• Model-based design for selecting fingerprint recognition algorithms for embedded systemsRosario Arjona, Iluminada Baturone. 579-582 [doi]
• Electrical characterization of a C-Element with LiChEnMatheus T. Moreira, Ney Laert Vilar Calazans. 583-585 [doi]
• Control and acquisition system for a High Dynamic Range CMOS Image SensorSonia Vargas-Sierra, Gustavo Liñán Cembrano, Ángel Rodríguez-Vázquez. 586-589 [doi]
• Long-term pulse stimulation and recording in an accelerated neuromorphic systemVasilis N. Thanasoulis, Johannes Partzsch, Bernhard Vogginger, Christian Mayr, René Schüffny. 590-592 [doi]
• Real-time FPGA connected component labeling systemElisa Calvo-Gallego, A. C. Aldaya, Piedad Brox, Santiago Sánchez-Solano. 593-596 [doi]
• A 500 MHz to 6 GHz frequency synthesizer architecture for cognitive radio applicationsZakaria El Alaoui Ismaili, Frederic Nabki, Wessam Ajib, Mounir Boukadoum. 597-600 [doi]
• Understanding large swing and low swing operation in DyCML gatesTiago Borges, Ernesto Ventura Martins, Luis Nero Alves. 601-604 [doi]
• A fully complementary and fully differential self-biased asynchronous CMOS comparatorVladimir Milovanovic, Horst Zimmermann. 605-608 [doi]
• Channel mismatch background calibration for pipelined time interleaved ADCsArmia Mrassy, Mohamed Dessouky. 609-612 [doi]
• A low-power single-slope analog-to-digital converter with digital PVT calibrationYuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa. 613-616 [doi]
• SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applicationsAnna Arbat, Cristiano Calligaro, Vladislav Dayan, Evgeny Pikhay, Yakov Roizin. 617-620 [doi]
• A practical method for modeling amplifier nonlinearitiesShafqat Ali, Steve Tanner, Pierre-André Farine. 621-624 [doi]
• Performances and trends in millimeter-wave CMOS voltage controlled oscillatorsMarius Voicu, Domenico Pepe, Domenico Zito. 625-628 [doi]
• A multi-valued 350nm CMOS voltage referenceNuno Lourenço, Luis Nero Alves, Jose Luis Cura. 629-632 [doi]
• Layout stress and proximity aware analog design methodologyA. Zein, A. Tarek, M. Bahr, M. Dessouky, H. Eissa, A. Ramadan, A. Tosson. 633-636 [doi]
• A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizerYoung-Min Park, Tae In Kwon, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn, Chang-Seob Shin, Myung-Jin Lee, Seung-Bin You, Ho-Jin Park. 637-640 [doi]
• A mixed-signal front-end ASIC for EEG acquisition systemHaiyan Zhou, Matthias Völker, Johann Hauer. 649-652 [doi]
• LC tank full bridge control for large coil variationsJosé Luis Merino, Catherine Dehollain. 653-656 [doi]
• Efficient area and power multiplication part of FFT based on twiddle factor decompositionSidinei Ghissoni, Eduardo Costa, José C. Monteiro, Ricardo Reis. 657-660 [doi]
• Offset measurement method for accurate characterization of BTI-induced degradation in opampsSwaraj Mahato, Pieter De Wit, Elie Maricau, Georges G. E. Gielen. 661-664 [doi]
• A study on MOSFET rectifiers with transistors operating in the weak inversion regionHugo B. Goncalves, Miguel A. Martins, Jorge R. Fernandes. 665-668 [doi]
• Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuitsMatheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans. 669-672 [doi]
• An ultra-low power current reused CMOS low noise amplifier for x-band space applicationSaeid Yasami, Magdy Bayoumi. 673-676 [doi]
• Utilization of multi-bit flip-flops for clock power reductionZhi-Wei Chen, Jin-Tai Yan. 677-680 [doi]
• Critical path minimized raster scan hardware architecture for computation of the Generalized Hough TransformFrank Schumacher, Markus Holzer, Thomas Greiner. 681-684 [doi]
• Flip-flop design using novel pulse generation techniqueFarshad Moradi, Dag T. Wisland, Jens Kargaard Madsen, Hamid Mahmoodi. 685-688 [doi]
• Dedicated hardware implementation of a linear congruence solver in FPGAJiri Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický. 689-692 [doi]
• Analog fault diagnosis and testing by inverse problem techniqueR. F. Ahmed, Ahmed Gomaa Radwan, Ahmed H. Madian, Ahmed M. Soliman. 693-696 [doi]
• A non-coherent BPSK receiver with dual band filtering for implantable biomedical devicesBenjamin P. Wilkerson, Jin-Ku Kang. 697-700 [doi]
• A new XOR-based Content Addressable Memory architectureLuca Frontini, Seyedruhollah Shojaii, Alberto Stabile, Valentino Liberali. 701-704 [doi]
• A low-complexity soft-decision decoding architecture for the binary extended Golay codePatrick Adde, Raphaël Le Bidan. 705-708 [doi]
• Fullwave-mode analysis of shielded microstrip discontinuities on anisotropic substratesOthmane Madani, Mohamed Lamine Tounsi, Mustapha Chérif-Eddine Yagoub. 709-712 [doi]
• Multiband integrated synthetic aperture radar (SAR) receiverFaizah Abu Bakar, Jan Holmberg, Tero Nieminen, Qaiser Nehal, Pekka Ukkonen, Ville Saari, Kari Halonen, Markku Åberg, Iiro Sundberg. 713-716 [doi]
• Low-power area-efficient delay element with a wide delay rangeJidan Al-Eryani, Alexander Stanitzki, Karsten Konrad, Nima Tavangaran, Dieter Brückmann, Rainer Kokozinski. 717-720 [doi]
• Skin effect modeling in time domain for RF network on chipLounis Zerioul, Emmanuelle Bourdel, Myriam Ariaudo. 721-724 [doi]
• Stochastic differential equations approach in the analysis of MTLs with randomly varied parametersLubomír Brancík, Edita Kolarova. 725-728 [doi]
• A RF/DC current-mode detector for BiST and digital calibration of current-driven mixersFeiran Lei, Vivek Yenamandra, Steven Bibyk, Mohammed Ismail. 729-732 [doi]
• A dual-axis bulk micromachined accelerometer with low cross-sensitivityAhmad Alfaifi, Frederic Nabki, Mourad N. El-Gamal. 733-736 [doi]
• TSV stress-aware performance and reliability analysisMuhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. 737-740 [doi]
• FFT implementation using QCAMuhammad Awais, Marco Vacca, Mariagrazia Graziano, Guido Masera. 741-744 [doi]
• Analysis of coupling capacitance between TSVs and metal interconnects in 3D-ICsKhaled Salah. 745-748 [doi]
• The leafs scan-chain for test application time and scan power reductionMaria Chalkia, Yiorgos Tsiatouhas. 749-752 [doi]
• Automatic selective hardening against soft errors: A cost-based and regularity-aware approachS. N. Pagliarini, Arwa Ben Dhia, Lirida Alves de Barros Naviner, Jean-François Naviner. 753-756 [doi]
• Transient fault analysis of CORDIC processorTing An, Matteo Causo, Lirida Alves de Barros Naviner, Philippe Matherat. 757-760 [doi]
• A new fault-tolerant architecture for CLBs in SRAM-based FPGAsArwa Ben Dhia, Lirida Alves de Barros Naviner, Philippe Matherat. 761-764 [doi]
• A monitoring infrastructure for FPGA self-awareness and dynamic adaptationCarlos Gómez Osuna, Miguel A. Sánchez Marcos, Pablo Ituero, Marisa López-Vallejo. 765-768 [doi]
• Adaptive disparity map computation for stereoscopic video watermarkingAfef Chammem, Mihai Mitrea, Françoise J. Prêteux. 769-772 [doi]
• Bayesian classification and artificial neural network methods for lung cancer early diagnosisFatma Taher, Naoufel Werghi, Hussain Al-Ahmad. 773-776 [doi]
• Sub-images based image hashing with non-negative factorizationSupakorn Prungsinchai, Fouad Khelifi, Ahmed Bouridane. 781-784 [doi]
• A study on the HEVC performance over lossy networksBasak Oztas, Mahsa T. Pourazad, Panos Nasiopoulos, Victor C. M. Leung. 785-788 [doi]
• 0.4V low-power 60-GHz oscillator in 65nm CMOSDomenico Pepe, Domenico Zito. 789-792 [doi]
• Complements on phase noise analysis and design of CMOS ring oscillatorsTimothy Cronin, Domenico Pepe, Domenico Zito. 793-796 [doi]
• A low-power all-digital PLL architecture based on phase predictionJingcheng Zhuang, Robert Bogdan Staszewski. 797-800 [doi]
• A dead-zone free and linearized digital PLLAmer Samarah, Anthony Chan Carusone. 801-804 [doi]
• Feasibility study including detector non-idealities of a 95-GHz CMOS SoC radiometer for passive imagingLorenzo Mereni, Domenico Pepe, Domenico Zito. 805-808 [doi]
• Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctionsVictor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes. 809-812 [doi]
• Validation and analysis of negative differential resistance of single-electron transistor with conductance modelXiaobao Chen, Zuocheng Xing, Bingcai Sui. 813-816 [doi]
• Low-noise dual-channel current amplifier for DNA sensing with solid-state nanoporesMarco Carminati, Giorgio Ferrari, Marco Sampietro, A. P. Ivanov, T. Albrecht. 817-820 [doi]
• CMOS Active Column Sensor for biodetection applications based on Surface Plasmon ResonanceA. Salazar, S. Camacho-Leon, Sergio Omar Martinez-Chapa, Olivier Rossetto. 821-824 [doi]
• Modeling and analysis of through silicon via: Electromagnetic and device simulation approachK. Salah, Alaa El Rouby, Hani Ragai, Yehea I. Ismail. 825-828 [doi]
• CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuitsSalim Farah, Magdy A. Bayoumi. 829-832 [doi]
• Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuitsHanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung. 833-836 [doi]
• Statistical leakage analysis using the deterministic modeling of cell leakage currentJae-Hoon Kim, Young-Hwan Kim. 837-840 [doi]
• Uncertainty in DLL deskewing schemesMonica Figueiredo, Rui L. Aguiar. 841-844 [doi]
• High-drive capability buffer for highly variable resistive loadsErika Covi, Alessandro Cabrini, Guido Torelli. 845-848 [doi]
• Should ΔΣ modulators used in AC motor drives be adapted to the mechanical load of the motor?Sergio Callegari, Federico Bizzarri. 849-852 [doi]
• Design of a low complexity S-box based on a piecewise linear chaotic mapDaisaburo Yoshioka. 853-856 [doi]
• On current control method for single-phase AC resistance spot weldingKang Zhou, Lilong Cai. 857-860 [doi]
• A brief analysis of the main SPICE models of the memristorJordi Albo-Canals, Giovanni Egidio Pazienza. 861-864 [doi]
• Field Programmable switched capacitor voltage converterChao Li, Jordi Cospi-Vilella, Herminio Martinez-Garcia. 865-868 [doi]
• A reconfigurable buck-boost switched capacitor converter with adaptive gain and discrete frequency scaling controlLibin George, Torsten Lehmann, Tara Julia Hamilton. 869-872 [doi]
• Design of a capacitorless low-dropout voltage regulator with fast load regulation in 130nm CMOSAntonio David Souza, Sergio Bampi. 873-876 [doi]
• Dedicated FPGA communication architecture and design for a large-scale neuromorphic systemVasilis N. Thanasoulis, Johannes Partzsch, Stephan Hartmann, Christian Mayr, René Schüffny. 877-880 [doi]
• Towards AER VITE: Building spike gate signalFernando Perez-Peña, Arturo Morgado Estevez, C. Rioja-Del-Rio, Alejandro Linares-Barranco, Angel Jiménez-Fernandez, Juan Lopez-Coronado, José Luis Muñoz-Lozano. 881-884 [doi]
• Picosecond pulse generation with nonlinear transmission lines in 90-nm CMOS for mm-wave imaging applicationsParamartha Indirayanti, Wouter Volkaerts, Patrick Reynaert, Wim Dehaene. 885-888 [doi]
• High level modeling of signal integrity in field bus communication with SystemC-AMSRuomin Wang, Julien Denoulet, Sylvain Feruglio, Farouk Vallette, Patrick Garda. 889-892 [doi]
• IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modellingAntonio Artés, José L. Ayala, Francky Catthoor. 893-896 [doi]
• 283)Shoaleh Hashemi Namin, Huapeng Wu, Majid Ahmadi. 897-900 [doi]
• A high-throughput ECC architectureEsmaeil Amini, Zahra Jeddi, Magdy Bayoumi. 901-904 [doi]
• Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspectiveRafael Westphal, José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos. 905-908 [doi]
• Second-order TDTL with initialization processMahmoud Al-Qutayri, Saleh R. Al-Araji, Jeedella S. Jeedella, Omar Al-Kharji Al-Ali, Nader Anani. 909-912 [doi]
• Encoding sequence design for a reduced complexity time synchronization approach for OFDM systemsLeïla Nasraoui, Leïla Najjar Atallah, Mohamed Siala. 913-916 [doi]
• Test setup for error vector magnitude measurement on WLAN transceiversVitor Fialho, Fernando Fortes, Manuela Vieira. 917-920 [doi]
• A hybrid algorithm for range estimation in RFID systemsKrishnamohan Thangarajah, Rashid Rashidzadeh, Shervin Erfani, Majid Ahmadi. 921-924 [doi]
• Discrete cosine transform Type-IV-based multicarrier modulators in frequency offset channelsPedro Amo-López, María Elena Domínguez Jiménez, Gabriela Sansigre Vidal, David Sanz de la Fuente, Fernando Cruz-Roldán. 925-928 [doi]
• A CMOS pixel sensor with 4-bit column-parallel self-triggered ADC for the ILC vertex detectorLiang Zhang, Frederic Morel, Christine Hu-Guo, Abdelkader Himmi, Andrei Dorokhov, Yann Hu. 929-932 [doi]
• A low noise high dynamic range analog front-end ASIC for the AGIPD XFEL detectorXintian Shi, Roberto Dinapoli, Dominic Greiffenberg, Beat Henrich, Aldo Mozzanica, Bernd Schmitt, Hans Krüger, Heinz Graafsma, Alexander Klyuev, Alessandro Marras, Ulrich Trunk. 933-936 [doi]
• Sense/drive architecture for CMOS-MEMS accelerometers with relaxation oscillator and TDCPiotr Michalik, Jordi Madrenas, Daniel Fernández. 937-940 [doi]
• Low power time-of-flight 3D imager system in standard CMOSPriyanka Kumar, Edoardo Charbon, Robert Bogdan Staszewski, Andre Borowski. 941-944 [doi]
• A double-delta compensating technique for pulse-frequency modulation CMOS image sensorTsung-Hsun Tsai, Richard Hornsey. 945-948 [doi]
• Design of adaptive nano/CMOS neural architecturesTeresa Serrano-Gotarredona, Bernabé Linares-Barranco. 949-952 [doi]
• Compact modeling for the transcapacitances of undoped or lightly doped nanoscale cylindrical surrounding gate MOSFETsNikolaos Fasarakis, Andreas Tsormpatzoglou, Dimitrios H. Tassis, Konstantinos Papathanasiou, C. A. Dimitriadis, G. Ghibaudo. 953-956 [doi]
• Estimating the starting point of conduction in nanoscale CMOS gatesDimitrios Tzagkas, Spiridon Nikolaidis, Abdoul Rjoub. 957-960 [doi]
• Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniquesLampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas. 961-964 [doi]
• Fast and accurate estimation of gain and unity-gain bandwidth of an OpAmpRodrigo Picos, Joan Font-Rosselló, Eugeni García-Moreno, Antonio E. Teruel. 965-968 [doi]
• FIR fractional Hilbert transformers with raised-cosine magnitude responseGoran Molnar, Mladen Vucic. 969-972 [doi]
• Conflict free, parallel memory access for radix-2 FFT processorsNikolaos Polychronakis, Dionysios I. Reisis, Emmanouil Tsilis, Ioannis Zokas. 973-976 [doi]
• An efficient 2-D jacobian iteration modeling for image interpolationAyush Kumar, Nimisha Agarwal, Juhi Bhadviya, Anil Kumar Tiwari. 977-980 [doi]
• A switching based adaptive image interpolation algorithmNimisha Agarwal, Ayush Kumar, Juhi Bhadviya, Anil Kumar Tiwari. 981-984 [doi]
• A highly parallelized processor for face detection based on Haar-like featuresHuabiao Qin, Lianbing Tian, Zongwei Hu. 985-988 [doi]