Abstract is missing.
- Process-variation and temperature aware soc test scheduling using particle swarm optimizationNima Aghaee, Zebo Peng, Petru Eles. 1-6 [doi]
- Novel Adaptive Virtual Channels technique for NoC switchRabab Ezz-Eldin, Magdy A. El-Moursy, Amr M. Refaat. 7-11 [doi]
- Survey of fault tolerance techniques for shared memory multicore/multiprocessor systemsHamid Mushtaq, Zaid Al-Ars, Koen Bertels. 12-17 [doi]
- Analog performance prediction based on archimedean copulas generation algorithmKamel Beznia, Ahcène Bounceur, Reinhardt Euler. 18-23 [doi]
- On modeling and optimizing cost in 3D Stacked-ICsMottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen. 24-29 [doi]
- Fault detection and diagnoses methodology for adaptive digitally-calibrated pipelined ADCsMohamed Abbas. 30-35 [doi]
- ReverseAge: An online NBTI combating technique using time borrowingSeyab Khan, Said Hamdioui. 36-41 [doi]
- Performance and functional test of flip-flops using ring oscillator structureRenato P. Ribas, André Inácio Reis, André Ivanov. 42-47 [doi]
- Validation & Verification of an EDA automated synthesis toolStefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto. 48-52 [doi]
- The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuitsLayla Hamieh, Nader Mehdi, Ghazalah Omeirat, Ali Chehab, Ayman I. Kayssi. 53-57 [doi]
- Layout-aware high performance interconnects for Network-on-Chip design in deep nanometer technologiesGursharan Reehal, Mohammed Ismail. 58-61 [doi]
- A Python-based layout-aware analog design methodology for nanometric technologiesStephanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander, Marie-Minerve Louërat. 62-67 [doi]
- An electrical-aware parametric DFM solution for analog circuitsRami Fathy Salem, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, Haitham Eissa, Mohamed Dessouky, David Nairn, Mohab H. Anis. 68-73 [doi]
- Yield enhancement flow for analog and full custom designs reliability-rules automatic applicationAhmad Abdulghany, Rami Fathy Salem, Luigi Capodieci, Shobhit Malik. 74-77 [doi]
- Bipolar OxRRAM memory array reliability evaluation based on fault injectionHassen Aziza, Marc Bocquet, Jean Michel Portal, Christophe Muller. 78-81 [doi]
- Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filtersAmir Hossein Gholamipour, Kyprianos Papadimitriou, Fadi J. Kurdahi, Apostolos Dollas, Ahmed M. Eltawil. 82-87 [doi]
- An area-efficient 2-D convolution implementation on FPGA for space applicationsStefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Gabriele Tiotto, Paolo Prinetto. 88-92 [doi]
- Digital circuits verification with consideration of destabilizing factorsRichard Goldman, Vazgen Melikyan, Eduard Babayan. 93-98 [doi]
- Design of tunable continuous-time quadrature bandpass delta-sigma modulatorsKhaled Sakr, Mohamed Dessouky, Abd-El Halim Zekry. 99-103 [doi]
- 4-D parity codes for soft error correction in aerospace applicationsMuhammad Imran, Zaid Al-Ars, Georgi Gaydadjiev. 104-109 [doi]
- Reduced dimension Vector Quantization encoding method for image compressionYan Wang, Amine Bermak, Farid Boussaïd. 110-113 [doi]
- Body contact based TSV equalizerKhaled Mohamed, Alaa El Rouby, Yehea I. Ismail, Hani Ragai. 114-117 [doi]
- RTL delay macro-modeling with Vt and Vdd variabilityTatsuya Koyagi, Sohaib Majzoub, Masahiro Fukui, Resve Saleh. 118-123 [doi]
- Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAMLe-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Abdullah Aljumah. 124-129 [doi]