Table of Contents

• Requirements and Concepts for Transaction Level Assertion RefinementWolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten. 1-14 [doi]
• Using a Runtime Measurement Device with Measurement-Based WCET AnalysisBernhard Rieder, Ingomar Wenzel, Klaus Steinhammer, Peter P. Puschner. 15-26 [doi]
• Implementing Real-Time Algorithms by using the AAA Prototyping MethodologyPierre Niang, Thierry Grandpierre, Mohamed Akil. 27-36 [doi]
• Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static PrioritiesKarsten Albers, Frank Bodmann, Frank Slomka. 37-46 [doi]
• Approach for a Formal Verification of a Bit-serial Pipelined ArchitectureHenning Zabel, Achim Rettberg, Alexander Krupp. 47-56 [doi]
• Automotive System Optimization using Sensitivity AnalysisRazvan Racu, Arne Hamann, Rolf Ernst. 57-70 [doi]
• Towards a Dynamically Reconfigurable Automotive Control System ArchitectureRichard Anthony, Achim Rettberg, De-Jiu Chen, Isabell Jahnich, Gerrit de Boer, Cecilia Ekelin. 71-84 [doi]
• An OSEK/VDX-based Multi-JVM for Automotive AppliancesChristian Wawersich, Michael Stilkerich, Wolfgang Schröder-Preikschat. 85-96 [doi]
• Towards Dynamic Load Balancing for Distributed Embedded Automotive SystemsIsabell Jahnich, Achim Rettberg. 97-106 [doi]
• Automatic Data Path Generation from C code for Custom ProcessorsJelena Trajkovic, Daniel Gajski. 107-120 [doi]
• Interconnect-aware Pipeline Synthesis for Array based Reconfigurable ArchitecturesShanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. 121-134 [doi]
• An Interactive Design Environment for C-based High-Level SynthesisDongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski. 135-144 [doi]
• Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software PartitioningScott Sirowy, Frank Vahid. 145-154 [doi]
• Embedded Vertex Shader in FPGALars Middendorf, Felix Mühlbauer, Georg Umlauf, Christophe Bobda. 155-164 [doi]
• A Hybrid Approach for System-Level Design EvaluationAlexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel. 165-178 [doi]
• Automatic Parallelization of Sequential Specifications for Symmetric MPSoCsFabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo. 179-192 [doi]
• An Interactive Model Re-Coder for Efficient SoC SpecificationPramod Chandraiah, Rainer Dömer. 193-206 [doi]
• Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization TechniqueM. B. Abdelhalim, A. E. Salama, S. E.-D. Habib. 207-220 [doi]
• Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded SystemsEdison Pignaton de Freitas, Marco A. Wehrmeister, Carlos Eduardo Pereira, Flávio Rech Wagner, Elias Teodoro Silva Jr., Fabiano Costa Carvalho. 221-230 [doi]
• Smart Speed Technology:::TM:::Mike Olivarez, Brian Beasley. 231-240 [doi]
• Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt ServicesGang Zeng, Hiroyuki Tomiyama, Hiroaki Takada. 241-254 [doi]
• Reducing the Code Size of Retimed Software Loops under Timing and Resource ConstraintsNoureddine Chabini, Wayne Wolf. 255-268 [doi]
• Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded SystemsMark Panahi, Trevor Harmon, Juan A. Colmenares, Shruti Gorappa, Raymond Klefstad. 269-278 [doi]
• Configurable Hybridkernel for Embedded Real-Time SystemsTimo Kerstan, Simon Oberthür. 279-288 [doi]
• Embedded Software Development in a System-Level Design FlowGunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer. 289-298 [doi]
• Data Reuse Driven Memory and Network-On-Chip Co-SynthesisIlya Issenin, Nikil Dutt. 299-312 [doi]
• Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus TransactionsRauf Salimi Khaligh, Martin Radetzki. 313-324 [doi]
• Hardware Implementation of the Time-Triggered Ethernet ControllerKlaus Steinhammer, Astrit Ademaj. 325-338 [doi]
• Error Containment in the Time-Triggered System-On-a-Chip ArchitectureRoman Obermaisser, Hermann Kopetz, Christian El Salloum, Bernhard Huber. 339-352 [doi]
• Generic Architecture Designed for Biomedical Embedded SystemsLeonel Sousa, Moisés Simões Piedade, J. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas. 353-362 [doi]
• A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill(EPill®)Dirk Jansen, Nidal Fawaz, Daniel Bau, Marc Durrenberger. 363-372 [doi]
• Utilizing Reconfigurable Hardware to Optimize Workflows in Networked NodesDominik Murr, Felix Mühlbauer, Falko Dressler, Christophe Bobda. 373-386 [doi]
• Dynamic Software Update of Resource-Constrained Distributed Embedded SystemsMeik Felser, Rüdiger Kapitza, Jürgen Kleinöder, Wolfgang Schröder-Preikschat. 387-400 [doi]
• Configurable Medium Access Control for Wireless Sensor NetworksLucas Francisco Wanner, Augusto Born de Oliveira, Antônio Augusto Fröhlich. 401-410 [doi]
• Integrating Wireless Sensor Networks and the Grid through POP-C++Augusto Born de Oliveira, Lucas Francisco Wanner, Pierre Kuonen, Antônio Augusto Fröhlich. 411-420 [doi]
• Modeling of Software-Hardware ComplexesK. H. (Kane) Kim. 421 [doi]
• Modeling of Software-Hardware ComplexesNikil Dutt. 423-425 [doi]
• Enhancing a Real-Time Distributed Computing Component Model through Cross-FertilizationK. H. (Kane) Kim. 427-430 [doi]
• Modeling of Software-Hardware ComplexesHermann Kopetz. 431-432 [doi]
• Software-Hardware Complexes: Towards Flexible BordersFranz-Josef Rammig. 433-435 [doi]
• Embedded SW Design Space Exploration and Automation using UML-Based ToolsFlávio Rech Wagner, Luigi Carro. 437-440 [doi]
• Medical Embedded SystemsRoozbeh Jafari, Soheil Ghiasi, Majid Sarrafzadeh. 441-444 [doi]