Abstract is missing.
- Temperature-Aware MicroarchitectureKevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan. 2-13 [doi]
- Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain MicroprocessorGrigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho. 14-25 [doi]
- Half-Price ArchitectureIlhyun Kim, Mikko H. Lipasti. 28-38 [doi]
- Iimplicitly-Multithreaded ProcessorsIl Park, Babak Falsafi, T. N. Vijaykumar. 39-50 [doi]
- MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture ConferencesDaniel Citron. 52-59 [doi]
- Banked Multiported Register Files for High-Frequency Superscalar MicroprocessorsJessica H. Tseng, Krste Asanovic. 62-71 [doi]
- Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply VoltageMichael D. Powell, T. N. Vijaykumar. 72-83 [doi]
- SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical SamplingRoland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe. 84-95 [doi]
- Transient-Fault Recovery for Chip MultiprocessorsMohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar. 98-109 [doi]
- ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded CodesMilos Prvulovic, Josep Torrellas. 110-121
- A Flight Data Recorder for Enabling Full-System Multiprocessor Deterministic ReplayMin Xu, Rastislav Bodík, Mark D. Hill. 122-133 [doi]
- A Highly-Configurable Cache Architecture for Embedded SystemsChuanjun Zhang, Frank Vahid, Walid A. Najjar. 136-146 [doi]
- Energy Efficient Co-Adaptive Instruction Fetch and IssueAlper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose. 147-156 [doi]
- Positional Adaptation of Processors: Application to Energy ReductionMichael C. Huang, Jose Renau, Josep Torrellas. 157-168 [doi]
- DRPM: Dynamic Speed Control for Power Mangagement in Server Class DisksSudhanva Gurumurthi, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke. 169-179 [doi]
- Token Coherence: Decoupling Performance and CorrectnessMilo M. K. Martin, Mark D. Hill, David A. Wood. 182-193 [doi]
- GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus NetworksArjun Singh, William J. Dally, Amit K. Gupta, Brian Towles. 194-205 [doi]
- Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory MultiprocessorsMilo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood. 206-217 [doi]
- Performance Analysis of the Alpha 21364-BAsed HP GS1280 MultiprocessorZarka Cvetanovic. 218-228 [doi]
- Parallelism in the Front-EndParamjit S. Oberoi, Gurindar S. Sohi. 230-240 [doi]
- Effective ahead Pipelining of Instruction Block Address GenerationAndré Seznec, Antony Fraboulet. 241-252 [doi]
- Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective ReplayDan Ernst, Andrew Hamel, Todd M. Austin. 253-262 [doi]
- Improving Dynamic Cluster Assignment for Clustered Trace Cache ProcessorsRavi Bhargava, Lizy Kurian John. 264-274 [doi]
- Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered ProcessorsRajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi. 275-286 [doi]
- A Pipelined Memory Architecture for High Throughput Network ProcessorsTimothy Sherwood, George Varghese, Brad Calder. 288-299 [doi]
- Efficient Use of Memory Bandwidth to Improve Network Processor ThroughputJahangir Hasan, Satish Chandra, T. N. Vijaykumar. 300-311 [doi]
- Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global HistoryRenju Thomas, Manoj Franklin, Chris Wilkerson, Jared Stark. 314-323 [doi]
- Detecting Global Stride Locality in Value StreamsHuiyang Zhou, Jill Flanagan, Thomas M. Conte. 324-335 [doi]
- Phase Tracking and PredictionTimothy Sherwood, Suleyman Sair, Brad Calder. 336-347 [doi]
- Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time SystemsAravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller. 350-361 [doi]
- DISE: A Programmable Macro Engine for Customizing ApplicationsMarc L. Corliss, E. Christopher Lewis, Amir Roth. 362-373 [doi]
- Building Quantum Wires: The Long and the Short of ItMark Oskin, Frederic T. Chong, Isaac L. Chuang, John Kubiatowicz. 374-385 [doi]
- Guided Region Prefetching: A Cooperative Hardware/Software ApproachZhenlin Wang, Doug Burger, Steven K. Reinhardt, Kathryn S. McKinley, Charles C. Weems. 388-398 [doi]
- Overcoming the Limitations of Conventional Vector ProcessorsChristoforos E. Kozyrakis, David A. Patterson. 399-409 [doi]
- A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing KernelsJinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French. 410-419 [doi]
- Exploiting ILP, TLP and DLP with the Polymorphous TRIPS ArchitectureKarthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore. 422-433 [doi]
- The Jrpm System for Dynamically Parallelizing Java ProgramsMichael K. Chen, Kunle Olukotun. 434-445 [doi]